Deconfigurable microprocessor architectures for silicon debug acceleration

Abstract

The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of "noise" in this phase is that large numbers of random test programs fail due to the same or similar design bugs. This redundant behavior adds long delays in the debug flow since each failing random program must be separately examined, although it does not usually bring new debug information. The development of effective techniques that detect dominant modes of failure among random programs and triage them into common categories eliminate redundant debug sessions and significantly boost silicon debug.We propose the employment of deconfigurable microprocessor architectures along with self-checking random test programs to reduce the redundant debug sessions and make the triage step of silicon debug more efficient. Several hardware components of high performance microprocessor micro-architectures can be deconfigured while keeping the functional completeness of the design. This is the property we exploit in our silicon debug methodology for the triaging of random test programs. We support our methodology by a hardware mechanism dedicated to silicon debug that groups the failing test programs into categories depending on the microprocessor hardware components that need to be deconfigured for a random test program to be correctly executed. Identical deconfiguration sequences for multiple test programs indicate the existence of redundancy among them and group them together. This grouping significantly reduces the number of failing tests that must be debugged afterwards. Detailed evaluation of the method on an x86 microprocessor demonstrates its efficiency in reducing the debug sessions and thus in accelerating silicon debug.

Methodologies for accelerated analysis of the reliability and the energy efficiency levels of modern microprocessor architectures

“…MARSSx86 is widely used for performance measurements [63] [64] [65] and utilizes PTLsim [13] to simulate the internal details of an x86-64 microprocessor model. PTLsim has been used for many reliability measurements [49] [57] [66], as well as silicon validation [67]. MARSSx86 is a full system, cycle-accurate simulator capable of simulating a multicore processor with a detailed implementation of the front-end and the back-end pipeline stages of a modern x86-64 architecture.…”

Methods for robust and energy - efficient microprocessor architectures

“…Other works contribute in difficult post-silicon validation issues, such as reducing error detection latencies in in-core bugs and cache consistency, but all of them require hardware modifications and neither method proposes solutions for the critical mechanism of address translation [117] [220]. The work presented in [213] combines self-checking validation programs (which can be generated by any of the previous approaches) with deconfigurable hardware structures to enhance root cause analysis of bugs inside the core, but it is also insufficient for detecting bugs in ATM.…”