Deep Level Transient Spectroscopy (DLTS) Study of 4H-SiC Schottky Diodes and PiN Diodes

Abstract

We have studied capacitance mode Deep Level Transient Spectroscopy (DLTS) of five 4H-SiC Schottky diode and PiN diode designs. Comparing with previous DLTS studies, we have identified four traps levels, Z1/2, EH1, EH3and EH5. Additionally, a new trap level, EH1, is prominent in blanket Al+and B+high-energy implanted samples but less so in mask-implanted samples. Al+implantation increases EH3(associated with silicon vacancy) and EH5, while B+implantation significantly reduces EH3. The Z1/2peak (associated with carbon vacancy) is reduced to very low levels after B+and Al+implantation.

Isothermal annealing study of the EH1 and EH3 levels in n-type 4H-SiC

“…Yet, since EH1 (EH3) and S1 (S2) levels share a very similar energy position in the band gap and similar annealing behavior [4,6], the EH1 (EH3) and S1 (S2) labeling is used interchangeably in the literature [4,7,10,17,[19][20][21][22]. The fact that energy levels have been indistinctly identified as either EH1 (EH3) or S1 (S2), irrespective of particle energy and type, has caused inconsistency in terms of microscopic identification of EH1 and EH3, e.g., their nature was associated either to carbon [4,13] or to silicon [17,23] displacement.…”

Dynamic Switching of 3kV 4H-SiC Charge-Balanced Junction Barrier Schottky (JBS) Diodes

“…The charge-balanced design concept for the drift region of unipolar power devices entails constructing a 3 dimensional network of buried p-type regions (CB-regions) surrounded by n-type regions with balanced doping concentrations in order to achieve an approximately rectangular electric field profile under blocking bias [3][4][5][6][7]. Implementation of the JBS diode structures on top of charge-balanced drift layer designs results in performance tradeoffs between forward voltage drop and switching parameters (Qrr, and others).…”