Deep Neural Network for Generation of the Initial Electrostatic Potential Profile

Han, Seung-Cheol; Hong, Sungmin

doi:10.1109/sispad.2019.8870521

Cited by 13 publications

(6 citation statements)

References 2 publications

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“…It is commonly shown in recent studies that artificial neural networks (ANNs) have a remarkable ability in capturing nonlinear relationships with high accuracy between electrical characteristics and device parameters. This indicates a substantial decrease in computation cost in estimating electrostatic potential [130,131], capacitance-voltage (CV) relationship, current voltage (IV) [132][133][134], V T [135], metal work function [136], as well as other figures of merit [137,138]. Furthermore, machine learning works well not only in the prediction of device characteristics but also in device optimization, where machine learning is coupled with a multi-objective optimization algorithm where the trade-off between electrical characteristics is carefully considered.…”

Section: Semiclassical Device Simulation With Aimentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Semiclassical Device Simulation With Aimentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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show abstract

“…Now, we review the related papers and compare the performance of each algorithm. Figure 5(a) shows the schematic of these works 13,[19][20][21] that used CNN-based model. The architecture originated in the generator of DCGAN, 22) a well-known model to generate images in the computer vision field.…”

Section: Process Simulationmentioning

confidence: 99%

“…Figure 8 shows the doping profile on the unstructured mesh that the deep learning model typically cannot deal with. Thus, many previous works 13,[18][19][20][21] have suggested converting such profiles into a structured mesh, as shown in Fig. 8(b).…”

Section: Process Simulationmentioning

confidence: 99%

“…However, the doping profile generated by the process simulation may be inefficient to use as an input of the deep learning models. Therefore, many existing studies, [12][13][14][15][16][19][20][21] have used simple scalar values that can represent the doping profile (i.e. the input value of the process simulation) as the input of deep learning.…”

Section: Device Simulationmentioning

confidence: 99%

“…First, with the architecture in Fig. 5, these studies, 13,[19][20][21] predicted the electrostatic potential across the transistors. After that, to obtain the carrier density, they proposed a strategy that solves the continuous equation with the fixed potential after the TCAD device simulation loads the electrostatic potential predicted by the deep learning model.…”

Section: Device Simulationmentioning

confidence: 99%

See 2 more Smart Citations

Comprehensive studies on deep learning applicable to TCAD

Myung

Choi

Jang

et al. 2023

Jpn. J. Appl. Phys.

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TCAD simulation has incessantly solved many complex problems, but it becomes demanding that alternatives be found because TCAD simulation cannot provide the precise and fast prediction in the nano-scale era. With the success story on deep learning in research area, many big data companies have attempted to introduce deep learning to support or replace TCAD simulation. The reason is deep learning models has great potential that solves the problems of the TCAD simulation in terms of execution time, coverage. This paper aims to describe various scenarios of deep learning applicable to TCAD. We firstly describe an application that supplies TCAD data to the deep learning model although TCAD simulation is not calibrated. We then review various approaches that mimic TCAD simulation itself. We finally introduce an application that deep learning model automatically calibrates TCAD models to the measurement without experts. In each scenario, we review the related papers and compare pros and cons.

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Using U-Net convolutional neural network to model pixel-based electrostatic potential distributions in GaN power MIS-HEMTs

Chen,

Hsiao,

Lin

et al. 2024

Sci Rep

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This study demonstrates a novel use of the U-Net convolutional neural network (CNN) for modeling pixel-based electrostatic potential distributions in GaN metal–insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with various gate and source field plate designs and drain voltages. The pixel-based images of the potential distribution are successfully modeled from the developed U-Net CNN with an error of less than 1% error relative to a TCAD simulated reference of a 500-V electrostatic potential distribution in the AlGaN/GaN interface. Furthermore, the modeling time of potential distributions by U-Net takes about 80 ms. Therefore, the U-Net CNN is a promising approach to efficiently model the pixel-based distributions characteristics in GaN power devices.

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Deep Neural Network for Generation of the Initial Electrostatic Potential Profile

Cited by 13 publications

References 2 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Comprehensive studies on deep learning applicable to TCAD

Using U-Net convolutional neural network to model pixel-based electrostatic potential distributions in GaN power MIS-HEMTs

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