Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Su, L.T.; Jacobs, J.B.; Chung, J.E.; Antoniadis, D.A.

doi:10.1109/55.291592

Cited by 47 publications

(20 citation statements)

References 7 publications

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“…The well-behaved subthreshold characteristics are results of thin channel silicon films (35 nm). It is also well known that FD-SOI devices have relatively low threshold voltage and high leakage currents without midgap workfunction gate materials [1]. Fig.…”

Section: Resultsmentioning

confidence: 99%

“…At short channel lengths, devices with 80 nm buried oxide show less DIBL compared to devices with 150 nm buried oxide. The decreased DIBL is a result of reduced coupling from drain and source to the channel due to better source and drain depletion charge termination through thinner buried oxide layers [1]. However, the parasitic junction capacitance of an SOI MOSFET degrades with thinner buried oxide thickness.…”

Section: Resultsmentioning

confidence: 99%

“…As FD-SOI MOSFET's are scaled to 0.18 m gate length, device design and process must be improved to control short-channel effects (SCE) and reduce parasitic source/drain resistance. In FD-SOI MOSFET's, the silicon thickness and buried oxide layer must be scaled with channel length to achieve acceptable short-channel performance [1]. For effective channel length around 0.1 m, channel thickness below 40 nm is needed to suppress SCE.…”

Section: Introductionmentioning

confidence: 99%

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0.18-μm fully-depleted silicon-on-insulator MOSFET's

Cao

Kamins

Voorde

et al. 1997

IEEE Electron Device Lett.

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High-performance 0.18-m gate-length fullydepleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance.Nominal device drive currents of 560 A/m and 340 A/m were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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0.18-μm fully-depleted silicon-on-insulator MOSFET's

Cao

Kamins

Voorde

et al. 1997

IEEE Electron Device Lett.

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“…The outstanding advantage of SOI MOSFETs is that the body overdoping becomes unnecessary, as CSE and DIBL are suppressed simply, by using thin enough films. 5,14,15 Because these effects occur in the transistor body, the properties of the buried insulator ͑thick-ness and dielectric constant͒ have a second-order impact. confirms the excellent control of the threshold voltage roll-off in 10 nm thick SOI MOSFETs: ⌬V T is maintained below 70-80 mV even in a 25 nm long channel.…”

Section: Short Channel Effects: Fringing Fields In Buried Aluminamentioning

confidence: 99%

SOI MOSFETs with Buried Alumina: Thermal and Electrical Aspects

Oshima¹,

Cristoloveanu²,

Guillaumot³

et al. 2004

J. Electrochem. Soc.

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To improve thermal dissipation in silicon-on-insulator metal-oxide-semiconductor field-effect transistors ͑SOI MOSFETs͒, we recently proposed replacing the buried oxide with buried alumina, which offers higher thermal conductivity. However, because alumina is a high-k insulator, there is also a definite impact on the electrical properties, namely, coupling and short-channel effects. Our simulations show that the role of fringing fields is accentuated, leading to more severe drain-induced barrier lowering ͑DIBL͒-like problems. The trade-off between the thermal merit and the electrical performance of very advanced SOI transistors is examined by comparing various MOS architectures. We conclude on the usefulness of a ground plane located underneath a relatively thin buried alumina.Silicon-on-insulator ͑SOI͒ technology has been included in the International Technology Roadmap of Semiconductors ͑ITRS͒ for two reasons: ͑i͒ enhanced performance of high-speed and/or lowpower complementary metal-oxide-semiconductor ͑CMOS͒ circuits and (ii) superior scalability. The future of bulk-Si MOS field-effect transistors ͑FETs͒ is unfortunately blocked by the necessity to continuously increase the doping level and reduce the junction thickness. The scaling rules are totally different for fully depleted SOI transistors, where the thin silicon film and buried oxide ͑BOX͒ can serve as additional tunable parameters. 1-5 The film thickness actually plays the dominant role and offsets the importance of film doping.The optimum film thickness is roughly one-third of the channel length. 6,7 This condition allows controlling the short-channel effects: threshold voltage roll-off, drain-induced barrier lowering ͑DIBL͒, subthreshold swing degradation, etc. A very thin Si film, t Si ϭ 5-15 nm only, is therefore required in deeply scaled SOI MOSFETs with 20-50 nm gate length.The problem with thinner Si films is that they aggravate the self-heating of SOI devices. The heat path through the source/drain regions is squeezed which increases the thermal resistance and causes the temperature to rise in the transistor body, as shown in Fig. 1. Self-heating in SOI MOSFETs is responsible for degradation in mobility, threshold voltage, subthreshold swing, leakage current, etc. 8 Because self-heating is due mainly to the poor thermal conductivity of the buried SiO 2 , an innovative solution we have proposed recently 9,10 is to replace the BOX with buried alumina or other dielectric, able to offer much improved thermal conductivity. The resulting structure is still SOI ͑thin Si-film, highly thermal conductive insulator, Si substrate͒, with the last letter of the acronym SOI becoming more meaningful. Such a material can be synthesized by adapting the current bonding techniques. 10 There are three basic steps: ͑i͒ alumina growth on a silicon wafer by atomic layer deposition, (ii) bonding to a passive wafer, and (iii) film thinning by Smart-Cut process or etchback. Prototype SOI structures with buried alumina have been manufactured and preliminary characterizat...

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“…Generally speaking, in order to suppress the short channel effect effectively, the SOI thickness (t SOI ) should be about a quarter of the gate length (L G ) in fully depleted SOI FETs with thick BOX [11], [12], and about a half in DG FETs. In ITRS 2008 update, it is expected that a FET with L G of 10 nm is in commercial mass production in 2015 [13], requiring FETs with t SOI of less than 3 nm.…”

Section: Introductionmentioning

confidence: 99%

Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultrathin Body nMOSFETs

Shimizu

Saraya

Hiramoto

2010

IEEE Electron Device Lett.

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Electron mobility in ultrathin body MOSFETs in double-gate (DG) operation has been investigated with SOI thickness of less than 4 nm for the first time. Although mobility degradation in DG compared to single gate occurs with SOI thickness of larger than 2 nm, the degradation is suppressed with SOI thickness of 1.7 nm. This suppression mechanism is explained by strong quantum confinement effect by an extremely thin SOI layer.Index Terms-Double gate (DG), electron mobility, MOSFET, SOI.

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Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Cited by 47 publications

References 7 publications

0.18-μm fully-depleted silicon-on-insulator MOSFET's

0.18-μm fully-depleted silicon-on-insulator MOSFET's

SOI MOSFETs with Buried Alumina: Thermal and Electrical Aspects

Suppression of Electron Mobility Degradation in (100)-Oriented Double-Gate Ultrathin Body nMOSFETs

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