Defect reduction in GaAs and InP grown on planar Si(111) and on patterned Si(001) substrates

Interface engineering for improved growth of GaSb on Si(111)

“…On Si (1 1 1) surfaces, a hexagonal interfacial misfit dislocation network may consist of partial dislocations [6][7][8]. In Fig.…”

Effect of Ga content on crystal shape in micro-channel selective-area MOVPE of InGaAs on Si

“…Si(111) substrates were used because the most flat and the most dislocation-free epilayer can be obtained on this orientation [3,7]. The SiO 2 layers were obtained by thermal oxidation of Si substrate with 100 nm thickness.…”

Advanced monolithic quantum well infrared photodetector focal plane array integrated with silicon readout integrated circuit

“…There are many methods that have been demonstrated to reduce the threading dislocation density of InP or GaAs on Si substrates: using a two-step growth method [18], growing a thicker InP buffer layer [19], using a short-period strained superlattice (e.g. GaAs/InAs) in the buffer layer, growing on patterned Si substrate [20], localized epitaxy overgrowth, or treating the buffer layer with ex situ or in situ thermal annealing [21]. Thermal annealing effectively reduces threading dislocation densities both in InP and GaAs epitaxial layers grown on Si by annihilation and coalescence of dislocations, which are caused by dislocation movement under the thermal stress induced by annealing [22].…”