“…Charge density trapping in the a-SiN X :H layer at or near the a-Si:H/a-SiN X :H interface (n t ) could be calculated through n t ϭC i (⌬V TE ϩ⌬V TH )/2q, 16 with C i presenting the insulator capacitance per unit area, in our case, it is 2.2 ϫ10 Ϫ8 F/cm 2 . Average n t of 6.1ϫ10 10 /cm 2 are trapped in the insulator after 10 000 s bias at 10 V. By using S ϭkT ln 10/q(1ϩq 2 N SS /C i ϩͱq 2 ⑀ Si N ds /C i ), [17][18][19] where C i , ⑀ Si , and q represent the insulator capacitance per unit area, the silicon dielectric constant, and absolute value of the electron charge, one gets the defect density in the conducting channel of an a-Si TFT, n ds ϭN ds ϫE G , through subthreshold ͑S͒, interface trapped defect density, n t ϭN SS ϫE G , and optical gap of a-Si:H͑D) E G , 1.7 eV. Since S E and S H change from 1.3 to 1.4 V/dec and 4.7 to 5.2 V/dec, respectively, after a 10 000 s bias stress at 10 V, the DOS increases from 3.31ϫ10 18 to 3.87ϫ10 18 /cm 3 and 4.72ϫ10 19 to 5.79 ϫ10 19 /cm 3 near the conduction and valence band mobility edge, respectively.…”