Defining Synthesizable OpenMP Directives and Clauses

Dziurzański, Piotr; Beletskyy, Volodymyr

doi:10.1007/978-3-540-24688-6_53

Cited by 7 publications

(4 citation statements)

References 6 publications

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“…Research has identified OpenMP as a suitable programming interface for HLS. Various works have identified applicable pragmas and preliminary guidelines [17], and proposed extensions [7], even translating to C-hardware-oriented languages [26]. Some solutions target hybrid architectures (general-purpose processors with FP-GAs) for embedded system design [14], but they only implement offload models without considering hierarchical (nested) parallelism when tasks are actually synthesized on the FPGA.…”

Section: Related Workmentioning

confidence: 99%

Software defined architectures for data analytics

Castellana

Minutoli

Tumeo

et al. 2019

Proceedings of the 24th Asia and South Pacific Design Automation Conference

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Data analytics applications increasingly are complex workflows composed of phases with very different program behaviors (e.g., graph algorithms and machine learning, algorithms operating on sparse and dense data structures, etc). To reach the levels of efficiency required to process these workflows in real time, upcoming architectures will need to leverage even more workload specialization. If, at one end, we may find even more heterogenous processors composed by a myriad of specialized processing elements, at the other end we may see novel reconfigurable architectures, composed of sets of functional units and memories interconnected with (re)configurable on-chip networks, able to adapt dynamically to adapt the workload characteristics. Field Programmable Gate Arrays are more and more used for accelerating various workloads and, in particular, inferencing in machine learning, providing higher efficiency than other solutions. However, their fine-grained nature still leads to issues for the design software and still makes dynamic reconfiguration impractical. Future, more coarse-grained architectures could offer the features to execute diverse workloads at high efficiency while providing better reconfiguration mechanisms for dynamic adaptability. Nevertheless, we argue that the challenges for reconfigurable computing remain in the software. In this position paper, we describe a possible toolchain for reconfigurable architectures targeted at data analytics.

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Section: Related Workmentioning

confidence: 99%

Software defined architectures for data analytics

Castellana

Minutoli

Tumeo

et al. 2019

Proceedings of the 24th Asia and South Pacific Design Automation Conference

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“…In [18], [19] the authors define which directives from OpenMP 2.0 can be synthetized. Furthermore, they implement a framework that generates SystemC code from OpenMP directives.…”

Section: Related Workmentioning

confidence: 99%

OpenMP extensions for FPGA accelerators

Cabrera

Martorell

Gaydadjiev

et al. 2009

2009 International Symposium on Systems, Architectures, Modeling, and Simulation

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Abstract-Reconfigurable computing is one of the paths to explore towards low-power supercomputing. However, programming these reconfigurable devices is not an easy task and still requires significant research and development efforts to make it really productive. In addition, the use of these devices as accelerators in multicore, SMPs and ccNUMA architectures adds an additional level of programming complexity in order to specify the offloading of tasks to reconfigurable devices and the interoperability with current shared-memory programming paradigms such as OpenMP. This paper presents extensions to OpenMP 3.0 that try to address this second challenge and an implementation in a prototype runtime system. With these extensions the programmer can easily express the offloading of an already existing reconfigurable binary code (bitstream) hiding all the complexities related with device configuration, bitstream loading, data arrangement and movement to the device memory. Our current prototype implementation targets the SGI Altix systems with RASC blades (based on the Virtex 4 FPGA). We analyze the overheads introduced in this implementation and propose a hybrid host/device operational mode to hide some of these overheads, significantly improving the performance of the applications. A complete evaluation of the system is done with a matrix multiplication kernel, including an estimation considering different FPGA frequencies.

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“…Dziurzanski and Beletskyy [3] first proposed the subseting and extending OpenMP for the purpose of hardware description. However, as far as we know, ours is the only actual implementation of OpenMP as a high level hardware description language via translations to Handel-C and VHDL.…”

Section: B Performance Of Vhdl Implementationmentioning

confidence: 99%

Generating hardware from OpenMP programs

Leow

Wong

2006

2006 IEEE International Conference on Field Programmable Technology

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Abstract-Various high level hardware description languages have been invented for the purpose of improving the productivity in the generation of customized hardware. Most of these languages are variants, usually parallel versions, of popular software programming languages. In this paper, we describe our effort to generate hardware from OpenMP, a software parallel programming paradigm that is widely used and tested. We are able to generate FPGA hardware from OpenMP C programs via synthesizable VHDL and Handel-C. We believe that the addition of this medium-grain parallel programming paradigm will bring additional value to the repertoire of hardware description languages.

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Defining Synthesizable OpenMP Directives and Clauses

Cited by 7 publications

References 6 publications

Software defined architectures for data analytics

Software defined architectures for data analytics

OpenMP extensions for FPGA accelerators

Generating hardware from OpenMP programs

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