Degradation analysis of high performance 14nm FinFET SRAM

Kraak, Daniël; Agbo, Innocent; Taouil, Mottaqiallah; Hamdioui, Said; Weckx, Pieter; Cosemans, Stefan; Catthoor, Francky

doi:10.23919/date.2018.8342003

Cited by 11 publications

(7 citation statements)

References 16 publications

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“…In both cases, this triggers read/write operations to/from the memory. These memory operations determine the workload of the memory and, thus, they strongly impact its aging [16], [17]. The idea proposed in this paper is to optimize the memory instructions issued by applications in order to mitigate the memory's aging.…”

Section: Proposed Methodologymentioning

confidence: 99%

Software-Based Mitigation for Memory Address Decoder Aging

Kraak

Gürsoy

Agbo

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

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Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory's address decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the address decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the address decoder logic. In particular, it reduces the degradation of the address decoder's setup delay by up to 43% with an execution overhead of only 1%.

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Section: Proposed Methodologymentioning

confidence: 99%

Software-Based Mitigation for Memory Address Decoder Aging

Kraak

Gürsoy

Agbo

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

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“…In [149], Song et al propose NCRTM, a run-time manager for improving the lifetime reliability of neuromorphic computing using PCM crossbars. Due to continuous use at elevated voltages, CMOS devices in the peripheral circuit of a crossbar suffer from bias temperature instability (BTI)-induced aging [150,151,152,153,154,39]. To improve reliability, it is necessary to periodically de-stress all neuron and synapse circuits in the hardware.…”

Section: System Software For Thermal and Reliability Optimizationmentioning

confidence: 99%

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Huynh¹,

Varshika²,

Paul³

et al. 2022

Preprint

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Recently, both industry and academia have proposed several different neuromorphic systems to execute machine learning applications that are designed using Spiking Neural Networks (SNNs). With the growing complexity on design and technology fronts, programming such systems to admit and execute a machine learning application is becoming increasingly challenging. Additionally, neuromorphic systems are required to guarantee real-time performance, consume lower energy, and provide tolerance to logic and memory failures. Consequently, there is a clear need for system software frameworks that can implement machine learning applications on current and emerging neuromorphic systems, and simultaneously address performance, energy, and reliability. Here, we provide a comprehensive overview of such frameworks proposed for both, platform-based design and hardware-software co-design. We highlight challenges and opportunities that the future holds in the area of system software technology for neuromorphic computing.

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“…For a fair analysis, the part of the memory's timing circuit that generates the enable signal for the decoder is also included. The reason for this is that aging of the timing circuit delays this enable signal and, thus, it partially compensates for the decoder's aging [18].…”

Section: A Experimental Setupmentioning

confidence: 99%

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder

Kraak

Agbo

Taouil

et al. 2019

2019 IEEE European Test Symposium (ETS)

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Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardwarebased mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

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Degradation analysis of high performance 14nm FinFET SRAM

Cited by 11 publications

References 16 publications

Software-Based Mitigation for Memory Address Decoder Aging

Software-Based Mitigation for Memory Address Decoder Aging

Implementing Spiking Neural Networks on Neuromorphic Architectures: A Review

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder

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