Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Xue, Min; Wang, Mingxiang; Zhu, Zhen; Zhang, Dongli; Wong, Man

doi:10.1109/ted.2006.888723

Cited by 47 publications

(36 citation statements)

References 22 publications

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“…In poly-Si TFTs, the device V th is determined to be the V g under which sufficient increase in channel mobility rather than channel charge inversion is obtained. [9], [19]. Therefore, this correlation of the µ FE shift with V th degradation can be explained by the stress-induced GB trap generation, which delays the increase in channel carrier mobility, similar to our previous observation for MILC poly-Si TFTs under HC stress [9].…”

Section: B Anomalous Field-effect Mobility Degradationsupporting

confidence: 87%

“…However, device reliability still remains a limiting factor for poly-Si TFTs toward future application in large-scale integration circuits. It is particularly true for MILC TFTs since, up to now, there are still rarely reported studies on their device reliability [8], [9]. It has been identified for poly-Si TFTs that hot carrier (HC) stress [4], [5], [9]- [14] and self-heating (SH) stress [4], [7], [9], [14]- [18] are two key mechanisms inducing device degradation.…”

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confidence: 99%

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Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Wang

Yang

et al. 2007

IEEE Trans. Electron Devices

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Abstract-Self-heating degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under various stress powers. A two-stage degradation behavior with turnaround effect at the initial stage is characterized. The initial degradation stage is related to breaking of weak Si-H bonds. The floating-body effect by released hydrogen ions is responsible for the observed backshift of the transfer curve during the initial stress. On the other hand, the normal degradation stage occurs by breaking of strong Si-Si bonds and trap generation at grain boundaries (GBs) and the gate oxide/channel interface. Our model is supported by observed different activation energies related to two degradation stages and a direct observation of the continuous increase in GB trap density during the normal degradation. Furthermore, during the normal degradation stage, an anomalous continuous field-effect mobility increase along with its V g dependence shift is first observed. It is clarified that this behavior is not a true channel mobility increase, but a consequence of stress-related trap generation.Index Terms-Field-effect mobility, metal-induced lateral crystallization, polycrystalline silicon (poly-Si), self-heating (SH) degradation, thin-film transistors (TFTs).

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Section: B Anomalous Field-effect Mobility Degradationsupporting

confidence: 87%

mentioning

confidence: 99%

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Wang

Yang

et al. 2007

IEEE Trans. Electron Devices

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“…The drain saturation current keeps almost constant while the drain saturation voltage increases with stress time significantly. Clearly, both transfer and output characteristic degradation features are consistent with typical HC degradation behaviors [9,10], implying that a HC mechanism should be involved.…”

Section: Degradation Phenomenasupporting

confidence: 57%

An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Zhang

Wang

2010

Microelectronics Reliability

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“…2. (2) In poly-Si TFTs, due to drain induced barrier lowering (DIBL) of HC induced trap potential barrier near the D, ON-state current degradation is reduced at a higher V d . 13 Such effect is absent in a-IGZO TFTs (data not shown here).…”

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confidence: 59%

Dynamic degradation of a-InGaZnO thin-film transistors under pulsed gate voltage stress

Wang

Shan

2015

Applied Physics Letters

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Instability of amorphous InGaZnO thin-film transistors under pulsed gate voltage (Vg) stress with steep transitions was experimentally investigated. The device threshold voltage (Vth) shifts positively depending on the number of pulse repetitions of the applied Vg pulses. For steeper pulse falling time (tf), more degradation occurs. In addition, for different base voltages of the Vg pulses, the maximum Vth degradation occurs under the condition that Vg pulses are symmetric about the flat band voltage. Such dynamic degradation is attributed to hot-carrier induced charge injection into the gate insulator and/or trapping at the interface near the source/drain regions during the tf transients.

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Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Cited by 47 publications

References 22 publications

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Dynamic degradation of a-InGaZnO thin-film transistors under pulsed gate voltage stress

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