Delay and noise estimation of CMOS logic gates driving coupled resistive–capacitive interconnections

Tang, K.T.; Friedman, Eby G.

doi:10.1016/s0167-9260(00)00005-5

Cited by 32 publications

(10 citation statements)

References 26 publications

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“…Here, in the static CMOS logic,increasing levels of device integration, die size, and operating frequency, a burgeoning portable and embedded computing and communications market, combined with reliability and packaging cost concerns, have made power dissipation a major issue in VLSI design. In complementary static CMOS, a popular VLSI logic style,power is primarily dissipated during logic transitions when gate loadcapacitances charge and discharge [10]. Also the number of transistors required in static logic family is two times the number of inputs which increases the occupied area-an undesirable characteristic where Though the static CMOS logic offers less speed, it is best known for its lowest power dissipation [7].…”

Section: Mechanismmentioning

confidence: 99%

Design High Performance Combinational Circuits Using Output Prediction Logic-OPL Technique

Dahiya¹,

Mittal²

2017

IOSR JECE

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Section: Mechanismmentioning

confidence: 99%

Design High Performance Combinational Circuits Using Output Prediction Logic-OPL Technique

Dahiya¹,

Mittal²

2017

IOSR JECE

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“…7, based on closed-form expressions for the line resistance, capacitance, and inductance [11], [12]. The criticality of the capacitive coupling is determined by the ratio of the coupling and self-capacitance, where an increase in the ratio results in increased capacitive coupling noise [15]. The maximum ratio occurs for narrow and close lines (see Fig.…”

Section: Dependence Of Coupling Noise On Layout Parametersmentioning

confidence: 99%

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

Vishnyakov

Friedman

Kolodny

2012

Microelectronics Journal

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“…Several models have been presented in the literature for calculating crosstalk noise effects analytically, instead of using nonlinear circuit simulation [4], [6], [22], [28]- [31]. These models use linearizations to approximate the behavior of a logic gate by a Thevenin voltage source in series with an effective linear output resistance, and a lumped RC network to approximate the distributed coupled wires.…”

Section: Noise Effects and Their Dependencementioning

confidence: 99%

“…The coupled noise voltage waveform might induce a logic hazard on a "quiet" victim net, leading to eventual logic failure. If noise is injected into a victim net during logic transition it can modify the victim's waveform, causing delay uncertainty [4]- [6] depending on the detailed behavior of aggressor signals. Consequently, a noncritical path might become a critical speed path, and clocking frequency may be limited by noise.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk noise reduction in synthesized digital logic circuits

Milter

Kolodny

2003

IEEE Trans. VLSI Syst.

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Abstract-As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Noncritical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.

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Delay and noise estimation of CMOS logic gates driving coupled resistive–capacitive interconnections

Cited by 32 publications

References 26 publications

Design High Performance Combinational Circuits Using Output Prediction Logic-OPL Technique

Design High Performance Combinational Circuits Using Output Prediction Logic-OPL Technique

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation

Crosstalk noise reduction in synthesized digital logic circuits

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