Abstract-Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.Index Terms-Integrated circuit interconnection, on-chip inductance, power distribution network, simultaneous switching noise.

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Abstmct-Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or lass than the time of flight delay of the signal through the low resistivity interconnect.In this paper, closed form expressions for the coupling noise between adjacent interconnect are presented to estimate the coupling noise voltage on a quiet line. These expressions are based on an assumption that the interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should preferably be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.

Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of flight delay of the signal through the interconnect. In this discussion, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver is modeled as a capacitor. A closed form expression for the coupling noise between adjacent interconnect is presented to estimate the coupling noise voltage on a quiet line based on the assumption that these interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.