Interconnect coupling noise in CMOS VLSI circuits

Tang, K.T.; Friedman, Eby G.

doi:10.1145/299996.300020

Cited by 30 publications

(9 citation statements)

References 13 publications

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“…Intra-chip interconnect coupling (capacitive and inductive coupling) is also significant in current single processors that form the multi-core system at the recent operating frequency of high performance processors [16], [17]. Although operating frequency in multi-core processor is being kept low (maximum that can be made without increasing power dissipation to threshold point), signal latency and signal distortion are still a major concern for the proper functioning of individual processors at this frequency range.…”

Section: Processormentioning

confidence: 99%

Multi-core processors: A new way forward and challenges

Roy

Chowdhury

2008

2008 International Conference on Microelectronics

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Abstract-Continuous effort to achieve higher performance without driving up the power consumption and thermal effects has led the researchers to look for alternative architectures for microprocessors. Like the parallel processing which is extensively used in today's all microprocessors, multicore architecture which combines several independent microprocessor cores in a single die has currently become very popular in most high performance intergraded circuits. Although multi-core processor offers excellent instruction execution speed with reduced power consumption, optimizing performance of individual processors and then incorporating them by interconnection on a single chip is a non-trivial task. This paper investigates the leading challenges associated with current high performance multi-core processor in terms of interfacing different cores, design automation and verification, software adaptability.

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Section: Processormentioning

confidence: 99%

Multi-core processors: A new way forward and challenges

Roy

Chowdhury

2008

2008 International Conference on Microelectronics

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“…Interconnect crosscapacitance noise is due to the charge injected into quiet/silent nets because of switching in neighboring nets through the coupling capacitance between them. The charge injected increases prominently in the deep submicron regime due to the increased coupling capacitance between adjacent nets causing reliability issues [Tang and Friedman 1999]. The noise due to coupling capacitance is the dominant component among noise sources and is a major concern in deep submicron design [Shanbhag et al 2000].…”

Section: Introductionmentioning

confidence: 99%

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Hanchate

Ranganathan

2004

ACM Trans. Des. Autom. Electron. Syst.

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The continuous scaling of interconnect wires in deep submicron (DSM) circuits results in increased interconnect delay, power, and crosstalk noise. In this work, we develop a game-theoretic framework and multimetric optimization algorithms for the simultaneous optimization during wire sizing of (i) interconnect delay and crosstalk noise, and (ii) interconnect delay, power, and crosstalk noise. We formulate the wire sizing optimization problem as a normal form-game model and solve it using Nash equilibrium theory. Game theory allows the optimization of multiple metrics with conflicting objectives. This property is exploited in modeling the wire sizing problem while simultaneously optimizing various design parameters like interconnect delay, power, and crosstalk noise, which are conflicting in nature. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled (i) as the geometric mean of interconnect delay and crosstalk noise in the case of first formulation, and (ii) as the weighted sum of interconnect delay, power, and crosstalk noise in the second formulation. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell. Complete information about the coupling effects among the nets is extracted after the detailed routing phase. The time and space complexities of the proposed wire sizing formulations are linear in terms of the number of net segments. Experimental results on several medium and large opencore designs indicate that the proposed algorithm for simultaneous optimization of interconnect delay and crosstalk noise yields an average reduction of 21.48% in interconnect delay and a 26.25% reduction in crosstalk noise without any area overhead, over and above the optimization from the Cadence place and route tools. It is shown through experimental results that the algorithm performs significantly better than simulated annealing and genetic search. Further, new simple but accurate models are developed for three parallel interconnect net segments. It is shown that these models yield the same level of accuracy with significantly better run times compared to the models reported in Chen et al. [2004]. A mathematical proof of existence for the Nash equilibrium solution for the proposed wire sizing formulation is also provided.

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“…Due to faster clock rate, the effect of inductance is going to be more pronounced in future technologies. Inductive and capacitive coupling make interconnect coupling noise significant [13]. Coupling noise between adjacent interconnects can cause disastrous effects on the logical functionality and long-term reliability of a VLSI circuit as well as complicate timing analysis.…”

Section: Introductionmentioning

confidence: 99%

Repeater and current-sensing hybrid circuits for on-chip interconnects

Maheshwari

Burleson

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI

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Designing interconnects is becoming an increasingly challenging problem with a few solutions. In this paper hybrid circuit based on the well known delay-optimal repeaters and the recently proposed differential current-sensing is presented. Comparison in terms of delay, power and area is drawn between various versions of the hybrid circuit with delay-optimal repeater insertion and differential current sensing in order to derive at the best possible solution. It is shown that driving 25% of the wire with repeaters and remaining with current-sensing is the best solution from delay standpoint (about 30% faster than delay-optimal repeaters). Not only do hybrid circuits consume less area, they are also a more acceptable solution from placement point of view due to fewer repeaters and a long segment of uninterrupted wire. Static power consumption inherited from differential current-sensing is the biggest drawback of the hybrid circuits.

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Interconnect coupling noise in CMOS VLSI circuits

Cited by 30 publications

References 13 publications

Multi-core processors: A new way forward and challenges

Multi-core processors: A new way forward and challenges

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Repeater and current-sensing hybrid circuits for on-chip interconnects

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