Delay and power expressions for a CMOS inverter driving a resistive-capacitive load

Adler, V.; Friedman, Eby G.

doi:10.1109/iscas.1996.541910

Cited by 24 publications

(29 citation statements)

References 16 publications

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“…A popularly and widely used alternative to complementary CMOS is pass transistor logic [8], which attempts to reduce the number of transistor required to implement logic by allowing the primary inputs to drive gate terminal as well as source drain terminal. This is contrast to logic family which only allows primary inputs to drive the gate terminal of MOSFET.…”

Section: B) Pass Transistor Logicmentioning

confidence: 99%

“…Also this logic style has advantages of high speed due to the small node capacitances, low power dissipation-as a result of the reduced number of transistors and lower interconnection effects due to a small area. However, most of the pass transistor logic implementations have two basic problems [8]. First, the threshold drop across the single-channel pass transistors results in reduced current drive and hence slower operation at reduced supply voltages.…”

Section: B) Pass Transistor Logicmentioning

confidence: 99%

“…Typical voltage swings for standard CMOS are from 3.3 to 5 volts with even smaller swings on the way [8]. All other thing being equal, equation (2) says that a smaller voltage swing will be proportionally faster.…”

Section: Introductionmentioning

confidence: 99%

“…The CMOS complementary gate has two function determining blocks an n-block and a pblock. There are normally 2n transistors in an n-input gate [8].…”

Section: Introductionmentioning

confidence: 99%

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Analysis of GDI Technique for Digital Circuit Design

Kumre¹,

Somkuwar²,

Agnihotri³

2013

IJCA

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Power Dissipation of Digital circuits can be reduced by 15% -25% by using appropriate logic restructuring and also it can be reduced by 40% -60% by lowering switching activity. Here, Gate Diffusion Input Technique which is based on a Shannon expansion is analyzed for minimizing the power consumption and delay of static digital circuits. This technique as compare to other currently used logic design style, allows less power consumption and reduced propagation delay for low-power design of combinatorial digital circuits with minimum number of transistors. In this paper, basic building blocks of digital system and few combinational circuits are analyzed using GDI and other CMOS techniques. All circuits are designed at 180nm technology in CADENCE and simulate using VIRTUOSO SPECTRE simulator at 100 MHz frequency. Comparative analysis has been done among GDI and other parallel design styles for designing ripple adder, CLA adder and bit magnitude comparator. Simulation result shows GDI technique saves 53.3%, 55.6% and 75.6% power in ripple adder, CLA adder and bit magnitude comparator respectively as compare to CMOS. Also delay is reduced with 25.2%, 3.4% and 6.9% as compare to CMOS. Analysis conclude that GDI is revolutionary high speed and low power consumption technique. General TermsLow power design, Digital circuit Design, VLSI, Logic Style.

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Section: B) Pass Transistor Logicmentioning

confidence: 99%

Section: B) Pass Transistor Logicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The CMOS complementary gate has two function determining blocks an n-block and a pblock. There are normally 2n transistors in an n-input gate [8].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analysis of GDI Technique for Digital Circuit Design

Kumre¹,

Somkuwar²,

Agnihotri³

2013

IJCA

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show abstract

“…As the density of circuit is increasing so power dissipation vital parameter in circuit designing. As the technology is advancing day by day, the need for low power dissipation and high speed had attracted many researchers [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

2017

IJSR

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Abstract:The two important issues in designing of analog circuits are area and power which can be controlled by various parameters.Addition is one of the important mathematical operations which serve as a building block. A low power full adder is the important circuit in the designing of other large circuits. In this paper, three low power full adders are designed using basic gate OR, AND, XOR and XNOR. These gates are designed by using GDI technique. When the number of transistors are decreased then the power consumption and area is reduced.GDI is a new technique for low power digital circuits .This techniques reduce the power consumption, propagation delay and transistor count of digital circuits. The adder cell consists of XOR and XNOR gates. The performance of different adder is compared in respect of various parameters. From results, its cleared that the due to less transistor count the power consumption and area is reduced DSCH and MICROWIND tool is used for the circuit design and simulation of it.

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Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison

Kumar

Hussain

Singh

2011

Computer Networks and Information Technologies

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Abstract. The paper presents a low power high speed Arithmetic Logic Unit (ALU) in 45 nm technology using Gate Diffusion Input (GDI) technique and its performance comparison with CMOS and nMOS Pass Transistor Logic (PTL) techniques. The simulated results revealed better performance characteristics of various logic and arithematic functions of a 1-bit ALU using GDI technique as compared to conventional CMOS and nMOS PTL techniques. GDI technique allows reducing power dissipation and delay while maintaining low complexity of logic design. MICROWIND and DSCH 3.1 EDA tools were used for the schematic layout and simulation of ALU using BSIM4 model.

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Delay and power expressions for a CMOS inverter driving a resistive-capacitive load

Cited by 24 publications

References 16 publications

Analysis of GDI Technique for Digital Circuit Design

Analysis of GDI Technique for Digital Circuit Design

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison

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