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Abstract.A delay and power model of a CMOS inverter driving a resistive-capacitive load is presented. The model is derived from Sakurai's alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time which exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads.

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented.

In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The proper insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. These repeaters are inserted within different types of common resistive interconnect structures, such as a line or a tree. In this paper, the application of repeaters to RC tree structures is discussed.A tree topology is a common interconnect structure frequently found in VLSI circuits. A short-channel transistor model is used as a foundation for the development of delay and power expressions to develop a design methodology for inserting repeaters into an RC tree network. Power dissipation expressions for these repeater structures are presented which consider both dynamic and short-circuit power. These design expressions are validated against simulated experiments with a maximum 11% and 16% deviation from SPICE for delay and power, respectively.