Repeater design to reduce delay and power in resistive interconnect

Adler, V.; Friedman, Eby G.

doi:10.1109/82.673643

Cited by 201 publications

(55 citation statements)

References 25 publications

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“…The implementation of such accurate delay circuitry is a challenging issue. We have 1 6 42 #2 1 2 87 #3 3 10.5 250 #4 3 15 410 employed the classic driver design [46] [47] to implement the delay generator circuit. Many researchers have extensively investigated how to achieve the optimal driver for long VLSI interconnects considering different objectives such as minimum delay, area or power consumption [45] [47].…”

Section: Delay Generator Circuitmentioning

confidence: 99%

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

Nourani

Attarha

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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Section: Delay Generator Circuitmentioning

confidence: 99%

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

Nourani

Attarha

Chakrabarty³

2002

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

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“…It is well known that wire delays grow quadratically as the length increases. A DWL approach, though created to save power, can be used to improve the speed of long word lines much like the repeater insertion in global interconnects [3], [4]. In addition, the grouping of cells into sub-rows and the size of the local buffers can be further exploited to improve the performance of all memory paths simultaneously.…”

Section: Introductionmentioning

confidence: 99%

Fast and Area-Efficient SRAM Word-Line Optimization

Stine

Guthaus

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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A word line driver controls the access of cells in a row in Static Random Access Memories (SRAMs) and has a significant impact on SRAM speed and power consumption. When gate delay is the dominant factor, simple models are a good guideline for fast word lines. However, routing wire delay is significant when the row size is large, which causes these designs to be suboptimal. This paper presents an analytical optimization technique using a delay model that includes gate delay, wire resistance, and wire capacitance to optimize high-performance word line driver topologies for SRAMs. The proposed methodology has a maximum 45% delay improvement and 42% buffer cost reduction.

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“…More concerns arise for especially long interconnects [5]. Repeaters, which divide a long interconnect into shorter sections, have been proposed and have successfully resolved the problems by improving the interconnect delay [6,7,8,9,10]. However, repeaters generate other problems: finding the optimal number and size of the repeaters has been nontrivial and additional power and area is required.…”

Section: Introductionmentioning

confidence: 99%

“…Particularly, following the input signal on its critical path, a boosting signal that is identical to the original input signal is routed to the inner gate of the IGAA device to lower V th in advance. When distributing the digital signals inside the chip, the most popular design approach for reducing propagation delay is to introduce intermediate repeaters in the interconnect line [6,7,8,9,10]. To decrease the interconnect delay in modern IC design, a long interconnect is divided evenly into smaller segments with repeaters inserted between each segment (each repeater is responsible for driving one segment).…”

Section: Interconnect Boosting Techniquementioning

confidence: 99%

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

Lee

Ryu

Kim

2015

IEICE Electron. Express

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Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore's law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAAbased designs. Keywords: gate-all-around (GAA), multi-gate transistor, interconnect, repeater, boosting technique, RC delay Classification: Integrated circuits References

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Repeater design to reduce delay and power in resistive interconnect

Cited by 201 publications

References 25 publications

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

Fast and Area-Efficient SRAM Word-Line Optimization

On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor

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