Delay Test for Diagnosis of Power Switches

Khursheed, Saqib; Shi, Kan; Al-Hashimi, Bashir M.; Wilson, Peter; Chakrabarty, Krishnendu

doi:10.1109/tvlsi.2013.2239319

Cited by 11 publications

(26 citation statements)

References 15 publications

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“…When moving from the leftmost segmentation setup to the right-most segmentation setup (Figure 4), the number of power switches L per SUT decreases and the observable delay M iC increases. This result complies with the findings of previous works [8], [9], [15], since SUTs of smaller size L delay the wake-up time. Consequently, the observable charging delay M ij depends on the segment size L. Yet, from Figure 4 we derive that M ij depends on additional factors that are discussed next.…”

Section: A Dependence Of Charging Delay On Segment Size Lsupporting

confidence: 93%

“…Finally, the observation logic requires |OP | observation cells and it is in the range [1,10] NAND gates for the ethernet circuit. Therefore, for the case of the ethernet, the proposed method leads to 55%-68% area overhead compared to the state-of-theart [15], which, however, is 0.41% the design size. The worst area overhead is 2.27% for the ring style of the s38584 circuit which is the smaller benchmark.…”

Section: Area Cost Evaluationmentioning

confidence: 96%

“…We examine both the ring and the grid power gating styles, shown in Figure 1(a) and in Figure 1(b), respectively. Based on this setup, in Section III, we show that the lumped model shortcut used by the state-of-the-art [8], [9], [15] may lead to both fault coverage loss and yield loss that may reach up to 67.7% and 25%, respectively, and we analyze the reasons of this test quality loss. To tackle this problem, Section IV presents a DFT architecture that considers a distributed PDNs model and restores the test quality (fault coverage and yield) at low cost.…”

Section: Introductionmentioning

confidence: 99%

“…Section VI evaluates the performance and presents the trade-offs of the proposed method and Section VII concludes the paper. Figure 2(a) presents the state-of-the-art DFT architecture for delay-based testing against stuck-open faults on header power switches [8], [9], [15]. The power switches are clustered in m segments-under-test (SUTs) of segment-size L power switches [9].…”

Section: Introductionmentioning

confidence: 99%

“…During the application phase, a single SUT S i is awakened by the control logic by deasserting the sleep i signal. Upon the capture moment, the NAND gate logic output is captured at the "test result" flip-flop by asserting the test clock [15], the frequency of which depends on the segment size L. The captured value indicates whether the observation point V V dd was sufficiently charged at the capture moment. Test clock frequency is selected based on the observable charging delay M of the V V dd point, hereafter referred to as observable wakeup time or simply observation M .…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Tenentes

Khursheed

Rossi

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk Abstract-This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuckopen faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-applicationtime and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

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Section: A Dependence Of Charging Delay On Segment Size Lsupporting

confidence: 93%

Section: Area Cost Evaluationmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Tenentes

Khursheed

Rossi

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Built‐in self test design of power switch with clock‐gated charge/discharge transistor

Chen

Bai

et al. 2014

IET Computers & Digital Techniques

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It is becoming common to implement header (footer) power switches in low-power system-on-chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built-in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic-high, the tested switches are fault-free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm 2. The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.

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High Quality Testing of Grid Style Power Gating

Tenentes

Khursheed

Al-Hashimi

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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Abstract-This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% testapplication-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

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Delay Test for Diagnosis of Power Switches

Cited by 11 publications

References 15 publications

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

Built‐in self test design of power switch with clock‐gated charge/discharge transistor

High Quality Testing of Grid Style Power Gating

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