Demonstrating delay-based reservoir computing using a compact photonic integrated chip

Abstract

Photonic delay-based reservoir computing (RC) has gained considerable attention lately, as it allows for simple technological implementations of the RC concept that can operate at high speed. In this paper, we discuss a practical, compact and robust implementation of photonic delay-based RC, by integrating a laser and a 5.4cm delay line on an InP photonic integrated circuit. We demonstrate the operation of this chip with 23 nodes at a speed of 0.87GSa/s, showing performances that is similar to previous non-integrated delay-based setups. We also investigate two other post-processing methods to obtain more nodes in the output layer. We show that these methods improve the performance drastically, without compromising the computation speed.

Scalable reservoir computing on coherent linear photonic processor

“…This is motivating the development of special-purpose AI hardware such as application-specific integrated circuits (ASICs) and fieldprogrammable gate arrays (FPGAs) 2,3 , which provide much faster and more energy-efficient computational resources. Recently, photonic implementations of artificial neural networks (ANNs) are attracting interest because they have great potential to reduce operational power, increase speed, and reduce latency beyond what is possible in electronic computing [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21] . Optical circuits can perform a large-scale multiply-accumulate (MAC) operation-a dominant factor in ANN computation-with ultrahigh processing speed thanks to their ultrawide bandwidth (terahertz region) and inherent parallelism in space, time, phase, and wavelength domains.…”

“…As pioneered by Shen et al, 4 it is possible to map the mathematical description of a neural network onto a photonic chip with external nonlinear devices. Up to now, photonic circuits have been reported for various ANN models, such as fully connected multilayer perceptrons [4][5][6] , spiking neural networks 7 , convolutional neural networks 8 , and recurrent neural networks, including reservoir computing (RC) [9][10][11][12][13][14][15][16][17][18][19][20][21] .…”

“…However, most conventional demonstrations have been limited to implementations of a middle recurrent layer called a "reservoir". The scalability for chip integration is highly limited due to their simple architectures (less than 23 neurons in the reservoir [14][15][16] ). In addition, the bandwidth is limited by the electrical components used for the nonlinear activation functions and input-output (I/O) frontend, such as response-lasers (gigahertz order) 12,15 and spatial light modulators (hertz order) 17 .…”

Experimental Investigation of an Optical Reservoir Computing System Based on Two Parallel Time-Delay Reservoirs

“…It is evident that for both tasks, the proposed RC system can double the DPR while maintaining a good performance compared with the system based on a single time-delay reservoir. Although the maximum potential DPR (200 MSa/s) achieved in this work does not reach to the state-of-the-art level (about 800 MSa/s) [22,23], the results demonstrate the feasibility of using an RC system with two parallel time-delay reservoirs to enable fast information processing.…”

“…Vatin et al successfully processed two tasks with a DPR of 51.3MSa/s (n = 492, θ = 0.08 ns) through a vertical-cavity surface-emitting laser based TDRC [16]. Based on a photonic integrated SL chip, Takano et al [22] and Harkhoe et al [23] achieve high DPRs of 0.806 GSa/s (n = 124, θ = 0.01 ns) and 0.87 GSa/s (n = 23, θ = 0.05 ns), respectively, which represent the state-of-the-art level of DPR for TDRC. However, further increasing the DPR of a TDRC system is very challenging, because for achieving such high DPRs, the system not only requires to further reduce the number of virtual nodes, but also requires a readout device (usually is a digital storage oscilloscope) with a sampling rate higher than tens of GSa/s.…”