Demonstration, Analysis, and Device Design Considerations for Independent DG MOSFETs

Masahara, Meishoku; Liu, Yongxun; Sakamoto, K.; Endo, Kazuhiko; Matsukawa, Takashi; Ishii, Keisuke; Sekigawa, Toshihiro; Yamauchi, H.; Tanoue, H.; Kanemaru, S.; Koike, Hideaki; Suzuki, Eiichi

doi:10.1109/ted.2005.855063

Cited by 132 publications

(78 citation statements)

References 16 publications

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“…1. Several studies have demonstrated independently controlled DG devices adopting FinFET-based technology [10]- [13]. Although modeling of the separated DG MOSFET is necessary, the threshold voltage model has yet to be fully developed.…”

Section: ψ(X Y) = A(x) + B(x)y + C(x)ymentioning

confidence: 99%

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Han¹,

Kim²,

Choi³

2008

IEEE Trans. Electron Devices

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Section: ψ(X Y) = A(x) + B(x)y + C(x)ymentioning

confidence: 99%

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Han¹,

Kim²,

Choi³

2008

IEEE Trans. Electron Devices

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“…the front gate and the back gate, are generally tied together. DG structures with independent gates have been proposed [2]- [3], having a four terminal operation. Independent DoubleGate (IDG) MOSFETs offer additional potentialities, such as a dynamic threshold voltage control by one of the two gates, transconductance modulation, signal mixer, in addition to the conventional switching operation.…”

mentioning

confidence: 99%

A compact model for the ballistic subthreshold current in ultra-thin independent double-gate MOSFETs

Munteanu

Moreau

Autran

2009

Molecular Simulation

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“…The γ in BG drive are very larger than those of TG drive. To achieve more detail analysis of γ and s.s., we compared γ of our data with theoretical approach done by M. Masahara et al [55], [56]. Their simple model is based on following assumption that, first, Si channel is thin and undoped single crystal, which is free from crystalline defects, and second, interface charge states between Si/SiO 2 and defects in SiO 2 are absent.…”

Section: Discussionmentioning

confidence: 93%

Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

Hara

Kamo

Satô

2014

IEICE Trans. Electron.

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SUMMARY Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below 550 • C, to realize high performance and low power dissipation system-onglass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5 µm and TG and BG SiO 2 thicknesses of 50 and 100 nm, respectively, exhibited a subthreshold swing of 120 mV/dec and a threshold voltage (V th ) of −0.5 V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor (γ = ∆V th /∆V BG ) of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from g m also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to the fabrication of high-speed and low power-dissipation SoG.

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Demonstration, Analysis, and Device Design Considerations for Independent DG MOSFETs

Cited by 132 publications

References 16 publications

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

A compact model for the ballistic subthreshold current in ultra-thin independent double-gate MOSFETs

Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

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