Demonstration of a Multi-Level μA-Range Bulk Switching ReRAM and its Application for Keyword Spotting

Wu, Y.; Cai, Fuxi; Thomas, L.; Liu, T.; Nourbakhsh, A.; Hebding, J.; Smith, E.; Quon, Roger; Smith, R.; Kumar, Arvind; Pang, A.; Holt, J.; Someshwar, R.; Nardi, Federico; Anthis, J.; Yen, S-H.; Chevallier, C.; Uppala, Apurva; Chen, X.; Breil, N.; Sherwood, Tyler; Wong, Kam W.; Cho, William; Thompson, David M.; Hsu, J.; Ayyagari, Buvna; Krishnan, Siddharth; Lü, Wei; Chudzik, M.

doi:10.1109/iedm45625.2022.10019450

Cited by 6 publications

(8 citation statements)

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“…Switching of f‐RRAM is typically abrupt and stochastic, since the conductance change is dominated by the movement of only a few ions in the conductive filaments. [ 6a,7b,14b ] In a recent work, [ 18 ] we introduced a non‐filamentary bulk RRAM (b‐RRAM) device, and showed that b‐RRAMs can be reliably programmed up to 128 levels between 400 nA and 4 µA (4–40 µS) across 300 mm wafer [ 18 ] (Figure S1, Supporting Information).…”

Section: Resultsmentioning

confidence: 99%

“…This particular phase has inherently high V O concentration, which is critical for forming‐free and bulk type switching. [ 18 ] More details on the device fabrication and material characterization can be found in. [ 16 ]…”

Section: Resultsmentioning

confidence: 99%

“…Recently, we reported a new class of forming‐free b‐RRAM featuring up to 128 programmable levels with high uniformity and yield across 300 mm wafers. [ 18 ] The device operates by modulating the profile of oxygen vacancy concentration in the bulk switching layer, therefore enabling gradual and precise programming without forming stage. A System‐on‐Chip (SoC) design that integrates 4 tiles of b‐RRAM crossbar arrays together with essential peripheral circuitry and a RISC‐V processor [ 9a ] have also been demonstrated for inference applications.…”

Section: Introductionmentioning

confidence: 99%

“…A System-on-Chip (SoC) design that integrates 4 tiles of b-RRAM crossbar arrays together with essential peripheral circuitry and a RISC-V processor [9a] have also been demonstrated for inference applications. [18] In this work, we apply the memristor-based CIM modules for DNN training tasks, using a recently proposed mixed-precision scheme. [15] The approach, based on a hybrid of CIM modules and digital systems, is shown in Figure 1, where the analog CIM performs VMM operations during forward propagation, and the gradient update during backpropogation is computed and accumulated in the high precision digital system.…”

Section: Introductionmentioning

confidence: 99%

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Bulk‐Switching Memristor‐Based Compute‐In‐Memory Module for Deep Neural Network Training

Wu,

Wang,

Wang

et al. 2023

Advanced Materials

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The need for deep neural network (DNN) models with higher performance and better functionality leads to the proliferation of very large models. Model training, however, requires intensive computation time and energy. Memristor‐based compute‐in‐memory (CIM) modules can perform vector‐matrix multiplication (VMM) in situ and in parallel, and have shown great promises in DNN inference applications. However, CIM‐based model training faces challenges due non‐linear weight updates, device variations, and low‐precision in analog computing circuits. In this work, we experimentally implement a mixed‐precision training scheme to mitigate these effects using a bulk‐switching memristor CIM module. Low‐precision CIM modules are used to accelerate the expensive VMM operations, with high precision weight updates accumulated in digital units. Memristor devices are only changed when the accumulated weight update value exceeds a pre‐defined threshold. The proposed scheme is implemented with a system on chip (SoC) of fully integrated analog CIM modules and digital sub‐systems, showing fast convergence of LeNet training to 97.73%. The efficacy of training larger models is evaluated using realistic hardware parameters and shows that that analog CIM modules can enable efficient mix‐precision DNN training with accuracy comparable to full‐precision software trained models. Additionally, models trained on chip are inherently robust to hardware variations, allowing direct mapping to CIM inference chips without additional re‐training.This article is protected by copyright. All rights reserved

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Bulk‐Switching Memristor‐Based Compute‐In‐Memory Module for Deep Neural Network Training

Wu,

Wang,

Wang

et al. 2023

Advanced Materials

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“…The pretrained weights are mapped as device conductance values scaled by device conductance range. Since RRAM devices support multibit mapping, [ 20 ] our experiments are based on devices with 16 conductance levels, i.e., 4‐bit precision, as shown in Figure 2c. Multibit inputs are supported using the bit‐serial input scheme.…”

Section: Cim System For Dnn Inference Accelerationmentioning

confidence: 99%

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

Wang,

Wu,

Park

et al. 2023

Advanced Intelligent Systems

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Analog compute‐in‐memory (CIM) systems are promising candidates for deep neural network (DNN) inference acceleration. However, as the use of DNNs expands, protecting user input privacy has become increasingly important. Herein, a potential security vulnerability is identified wherein an adversary can reconstruct the user's private input data from a power side‐channel attack even without knowledge of the stored DNN model. An attack approach using a generative adversarial network is developed to achieve high‐quality data reconstruction from power leakage measurements. The analyses show that the attack methodology is effective in reconstructing user input data from power leakage of the analog CIM accelerator, even at large noise levels and after countermeasures. To demonstrate the efficacy of the proposed approach, an example of CIM inference of U‐Net for brain tumor detection is attacked, and the original magnetic resonance imaging medical images can be successfully reconstructed even at a noise level of 20% standard deviation of the maximum power signal value. This study highlights a potential security vulnerability in emerging analog CIM accelerators and raises awareness of needed safety features to protect user privacy in such systems.

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Hardware implementation of memristor-based artificial neural networks

Aguirre,

Sebastian,

Le Gallo

et al. 2024

Nat Commun

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Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

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Demonstration of a Multi-Level μA-Range Bulk Switching ReRAM and its Application for Keyword Spotting

Cited by 6 publications

References 0 publications

Bulk‐Switching Memristor‐Based Compute‐In‐Memory Module for Deep Neural Network Training

Bulk‐Switching Memristor‐Based Compute‐In‐Memory Module for Deep Neural Network Training

PowerGAN: A Machine Learning Approach for Power Side‐Channel Attack on Compute‐in‐Memory Accelerators

Hardware implementation of memristor-based artificial neural networks

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