Demonstration of fully‐vertical GaN‐on‐Si power MOSFETs using regrowth technique

Abstract

The authors are reporting for the first time the fabrication of GaN-based fully-vertical high-power metal-oxide-semiconductor field effect transistors on Si. The electrical measurements of the fabricated device exhibited both vertical and lateral modes of operation. The transfer characteristics of the device in vertical mode showed a peak trans-conductance (G m, max) of 23.6 mS/mm with a threshold voltage (V th) of −19.6 V. The maximum current drain density (I D, max) of 249.3 mA/mm was observed with ON-resistance (R ON) of 44.2 V-mm. The electrical results obtained in the vertical mode were also compared with the laterally oriented devices. The comparison of the electrical results indicates a relatively higher ON-resistance of the device in the vertical configuration, due to the contribution of the series resistance of the buffer layers in the epi-structure.

On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs

“…Therefore, a significant cost reduction down to ~10 USD / cm 2 is predicted for large scale production. Recently, fully vertical GaN-on-Si power MOSFETs [14] [15] and quasi-vertical FinFETs on engineered substrates [16] were demonstrated as a solution for low cost large wafer size but these solutions need additional sophisticated substrate removal or back etching technologies.…”

Current Trends in the Development of Normally-OFF GaN-on-Si Power Transistors and Power Modules: A Review

“…The controllability and the cost effectiveness of the selectively p-GaN growth remain the main challenges. [31][32][33][34][35] Recent efforts to increase the power density of GaN-on-Si technology have resulted in fully vertical devices 17,[48][49][50] and the FinFET structure. 50,51 Lowresistance vertical conduction paths require modification of the epitaxial layers.…”

Epitaxial regrowth and characterizations of vertical GaN transistors on silicon

“…Initially, the epitaxial structure contained of (bottom-to-top) an ultrathin 3 nm Si-doped AlN layer, a 3.3 μm thick highly-doped (Si: 2×10 19 cm −3 ) n + -GaN (28 nm)/AlN (5 nm) strained layer superlattice (SLS), a 1 μm thick n − -GaN drift layer (Si: 2×10 16 cm −3 ) and a 0.1 μm-thick p-GaN (Mg: 5×10 19 cm −3 ) layer. In the epi-layer structure, the growth temperature of the 3-nm AlN layer on Si was 1030 °C, whereas, the rest of the epitaxial layers were grown at 1130 °C [21]. At the starting of the epitaxial regrowth process, a 0.4-μm-deep selective anisotropic gate trench etching was done using BCl 3 -based inductively coupled plasma reactive ion etching (ICP-RIE) at the power of 30 W, to form a p-GaN aperture for the vertical current in the device.…”

“…Recently, our research group has demonstrated a method to improve the forward resistance by inserting a heavily Si-doped ultra-thin AlN initial layer on Si and a 3.3 μm-thick conductive n + -GaN/AlN strained layer superlattice (SLS) structure in a fully-vertical structure of a GaN p-n diode on Si [19,20]. A similar buffer layer structure was also employed to develop the GaN-based fully-vertical metal-oxide-semiconductor field-effect transistors (V-MOSFETs) on Si to investigate primitive electrical characteristics of the devices [21]. Because of the highly doped buffer structure, our epi-structures are capable to overcome the vertical conduction issue without any further complicated processes.…”