Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

Enabling Power-Efficient Designs with III-V Tunnel FETs

“…1). Knoll et al [4] demonstrated the first strained Si nanowire inverter showing sharp transition at 0.2 V. Considering the low tunneling current of Si TFETs, III-V semiconductor materials offer more freedom of engineering the tunnel junctions and improving the tunneling current [5]. Dewey et al in [6] first explored InGaAs homojunction and heterojunction TFET (HTFET) with improved on-current than Si TFET.…”

Experimental demonstration of improved analog device performance of nanowire-TFETs

“…In contrast to the heavy As + in the first device generation the P + ion implantation created less crystal defects and more P atoms are activated at low temperature and by that improve the tunneling junction quality. Further details on the TFET fabrication process are described in [14]. Fig.…”

“…The epitaxial NiSi 2 layers were formed using very thin Ni layers at source/drain. Steep n + -i-source and p + -i junctions with 1.4 nm/dec and 3.5 nm/dec were realized by tilted implantation of As + -ions and B + -ions, respectively followed by low temperature annealing to segregate dopants at the NiSi 2 /channel interfaces [14].…”

Unique reliability characteristics of fully depleted silicon-on-insulator tunneling FET

“…However, the low current drivability has been pointed as the major weakness of TFET. To improve the performance of TFET (e.g., the decrease of SS and increase of I ON =I OFF ratio), extensive research has been performed using various approaches, including the modification of the device structure, [3][4][5][6][7][8] introduction of new materials, [9][10][11][12] and optimization of the fabrication technology. [13][14][15][16][17] Studies have also investigated many of the TFET-based circuit designs.…”