Abstract-Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (V dd ) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy-delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2× energy increase can be traded off for a ∼1.5× reduction in relay delay. A contact-gap-toactuation-gap thickness ratio of 0.7-0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide > 10× energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to ∼100 MHz.Index Terms-Digital integrated circuits, logic devices, low power circuit, microelectromechanical systems, microswitches, subthreshold slope, 60 mV/dec.