Seesaw Relay Logic and Memory Circuits

Jeon, Jong-June; Pott, V.; Kam, Hei; Nathanael, Rhesa; Alon, Elad; Liu, Tsu‐Jae King

doi:10.1109/jmems.2010.2049826

Cited by 37 publications

(22 citation statements)

References 10 publications

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“…For example, when the voltage applied to IN is GND, the suspended output electrode will be deflected into contact with both D 1 and the fixed output electrode (OUT). It should be noted that this switch design is a variant of the laterally actuated 6-T relay design in [14], which is identical in function to the vertically actuated seesaw relay design introduced in [19] and experimentally demonstrated to perform basic logic functions in [20] consistent with Fig. 2.…”

Section: A Switch Design Considerationsmentioning

confidence: 96%

Microelectromechanical Relay and Logic Circuit Design for Zero Crowbar Current

Fujiki

Hutin

et al. 2014

IEEE Trans. Electron Devices

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A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated.

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Section: A Switch Design Considerationsmentioning

confidence: 96%

Microelectromechanical Relay and Logic Circuit Design for Zero Crowbar Current

Fujiki

Hutin

et al. 2014

IEEE Trans. Electron Devices

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“…Since only one deposition step is involved in the laterally actuated switch fabrication, metallic material is most favorable for its low process temperature and low resistivity. As most of the device failures happen in the contact area, including welding, material transfer, delamination, and destruction [35], metal of high hardness and high melting point are commonly used, such as ruthenium [36]- [39], tungsten [40]- [42].…”

Section: Design Considerationmentioning

confidence: 99%

Pull-In Voltage and Fabrication Yield Analysis of All-Metal-Based Nanoelectromechanical Switches

Qian

Soon

Lee

2015

J. Microelectromech. Syst.

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We designed a one-mask process for all-molybdenum-based laterally actuated nanoelectromechanical switches. The damascene-like process is designed to ensure a smooth, high-aspect ratio, and metal-to-metal mechanical contact. Based on the statistical study of 800 devices, very high process yield can be achieved for fixed-fixed beam devices by selecting suitable device dimensions, i.e., the beam length versus beam width ratio should be <70 and the ratio of actuation gap to contact gap should be >1.5. Typical failure modes are also discussed.[ 2014-0391]Index Terms-Switches, nanoelectromechanical systems, electrostatic devices. I. INTRODUCTIONE LECTROSTATICALLY actuated micro/nano electromechanical system (M/NEMS) switches have been attracting attention for their excellent switching properties including zero-leakage current, abrupt switch behavior and potential to operate in high temperature [1]- [5]. These unique properties make NEMS switch a strong candidate for ultra-low power electronics and harsh environment integrated circuit (IC) [6]-[10].On the other hand, it would be difficult for NEMS switches to entirely replace CMOS transistors in high performance ICs, since NEMS switches have lower a operating frequency due to their large mechanical delay. To avoid the low speed NEMS switches slowing down the circuit and fully utilize their zero leakage properties, several applications have been proposed for NEMS-CMOS integration, by using NEMS switches to replace speed insensitive elements in field programmable gate array [11]-[15], power gating [16]-[18] and static random access memory [19]-[21]. Studies indicate that introducing NEMS switches would largely reduce the power consumption of the whole NEMS-CMOS IC. To realize hybrid NEMS-CMOS circuit [22], [23], directly fabricating NEMS switches on top of CMOS layer would be a realistic and cost-effective technique. The semiconductor industry has developed air gap back end process [24] which is most suitable for the NEMS-CMOS hybrid circuit. Manuscript

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“…inverter. Seesaw-relay-based logic and memory circuits have been demonstrated in [23] capable of performing an INVERTER, AND and OR gates. A torsional two layer MEMS logic gate has been reported in [24,25], which is able to perform NAND and NOR operations using a single device structure.…”

mentioning

confidence: 99%