Demonstration of L-Shaped Tunnel Field-Effect Transistors

Kim, Sang Wan; Kim, Jang Hyun; Liu, Tsu‐Jae King; Choi, Woo Young; Park, Byung‐Gook

doi:10.1109/ted.2015.2472496

Cited by 281 publications

(160 citation statements)

References 19 publications

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“…So, the non-local BTBT can model the tunneling process more accurately [17]. A lot of work has demonstrated that TFETs simulated by non-local BTBT are in accord with the experiments [8, 10, 18]. Since the source regions are highly doped, the band gap narrowing model and Fermi-Dirac statistics are included.…”

Section: Methodsmentioning

confidence: 99%

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate

Liu

Wang

et al. 2017

Nanoscale Res Lett

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In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

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Section: Methodsmentioning

confidence: 99%

Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate

Liu

Wang

et al. 2017

Nanoscale Res Lett

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“…As depicted in Fig. 3(a), the BTBT is not occurred until the conduction band edge (E C ) at the interface of epitaxial Si / gate dielectric is aligned with the valence band edge (E V ) at the source [3]. Consequently, RTFET has higher BTBT probability at V turn-on , resulting in more abrupt on / off transition than planar TFET.…”

Section: Device Structure and Processmentioning

confidence: 99%

“…Tunnel field-effect transistor (TFET) has been regarded as a promising candidate for future eneryefficient device because it can achieve steep subthreshold swing (S) [1][2][3][4]. However, there are several impediments for its commercialization: relatively low on-current (I on ) due to its limited band-to-band tunneling (BTBT) junction area defined by shallow inversion layer, unwanted ambipolar leakage current (I amb ) due to BTBT at drain junction [5] and short-channel effect (SCE) such as drain-induced barrier thinning (DIBT) [6] and sourceto-drain direct tunneling.…”

Section: Introductionmentioning

confidence: 99%

“…However, there are several impediments for its commercialization: relatively low on-current (I on ) due to its limited band-to-band tunneling (BTBT) junction area defined by shallow inversion layer, unwanted ambipolar leakage current (I amb ) due to BTBT at drain junction [5] and short-channel effect (SCE) such as drain-induced barrier thinning (DIBT) [6] and sourceto-drain direct tunneling. During last decade, several studies have been carried out to address those technical issues, especially for high on-off current ratio (I on / I off ) [3,[7][8][9]. Among them, the device structure, which feature BTBT perpendicular to the channel direction, are very attractive in terms of high I on and low S becuase their BTBT junction area (A t ) and barrier width (W t ) are defined by geometrical design parameters [3,9].…”

Section: Introductionmentioning

confidence: 99%

“…During last decade, several studies have been carried out to address those technical issues, especially for high on-off current ratio (I on / I off ) [3,[7][8][9]. Among them, the device structure, which feature BTBT perpendicular to the channel direction, are very attractive in terms of high I on and low S becuase their BTBT junction area (A t ) and barrier width (W t ) are defined by geometrical design parameters [3,9]. On the other hand, the recessed-channel structure is very helpful to address SCE with the help of increased physical channel length.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Recessed-channel Tunnel Field-Effect Transistor (RTFET) with the Asymmetric Source and Drain

Kwon¹,

Kim²,

Lee³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shortchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computeraided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ~446´ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

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