2017
DOI: 10.1186/s11671-017-1958-3
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Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate

Abstract: In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads… Show more

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Cited by 68 publications
(47 citation statements)
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“…As a result, SS avg of 42.8 mV/decade and I ON of 10 −6 A/μm can be achieved by L-TFET. To further improve the performance of TFETs, an improved TG-TFET with T-shaped overlap and dual source is reported [20,21]. As a result, the I ON of TG-TFET reaches 81 μA/ μm.…”
Section: Introductionmentioning
confidence: 99%
“…As a result, SS avg of 42.8 mV/decade and I ON of 10 −6 A/μm can be achieved by L-TFET. To further improve the performance of TFETs, an improved TG-TFET with T-shaped overlap and dual source is reported [20,21]. As a result, the I ON of TG-TFET reaches 81 μA/ μm.…”
Section: Introductionmentioning
confidence: 99%
“…However, small ON-state current and large Miller capacitance are still inherent disadvantages in TFETs. To improve the ON-state current, a lot of novel structures of TFETs are proposed, for example, the L-shaped channel TFET (LTFET) [5][6][7], U-shaped channel TFET (UTFET) [8,9], symmetric TFET (S-TFET) [10,11], U-shaped channel with dual sources TFET (DS-UTFET) [12], covered source-channel TFETs (CSC-TFETs) [13], hetero junction TFET with T-shaped gate (HTG-TFET) [14], 2D materials channel TFET and hetero-bilayer TFETs [15,16]. As a whole, TFETs reported in recent years adopt abrupt junction at tunneling interface, which leads to a complex fabrication processes and a high thermal budget.…”
Section: Introductionmentioning
confidence: 99%
“…However, there are also inherent disadvantages in TFETs, the most serious problems are small ON-state current and large miller capacitance. To address these issues, a lot of novel structures of TFETs are proposed [8][9][10][11][12][13][14][15][16][17][18][19]. As a whole, most of TFETs reported in recent years adopt different doping concentration in channel and active regions to form heavily doped abrupt junction at tunneling interface, which leads to a complex fabrication processes and a high thermal budget, what's more, introduction of high-density layer at source/channel junction and Gaussian doping in drain region also find difficultly during fabrication process and it's easy to be influenced by random dopant fluctuations (RDFs) [20][21][22][23].…”
Section: Introductionmentioning
confidence: 99%