A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

Chen, Shupeng; Wang, Shulong; Liu, Hongxia; Han, Tao; Xie, Hong‐Guang; Chen, Chong

doi:10.1186/s11671-020-03429-3

Cited by 30 publications

(15 citation statements)

References 38 publications

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“…Moreover, both the left-sided and right-sided channel thickness (where the tunneling is taking place) of the proposed device are limited to 5 nm. The 5nm channel thickness based on charge plasma in the line TFET has also been followed by [63,64]. However, a correct computation of 2D electron-hole concentration and their proper adoption of the quantization model become very necessary due to the small 5 nm t Si .…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

et al. 2023

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In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source/drain region. Due to its doping-less structure, the proposed CP-ITSM-DLTFET is immune to random dopant fluctuations and does not require an expensive thermal annealing technique. This makes the proposed device’s fabrication easier and more efficient. The proposed CP-ITSM-DLTFET comprises an inverted T-shaped source metal (sandwiched between the Si-channel) and creates gate-to-source overlap and increases the tunneling area vertically on both sides of the Si-channel. The vertical line-tunneling area in the proposed structure makes the device able to be aggressively scaled compared to conventional TFETs for future technology. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. The switching performance (like high ION=31.88uA/um, steeper AVSS=23.42mV/dec (over 12-order of drain current), and high ION/IOFF ratio of 1.6×1013) and the RF performance (like, transconductance (gm)=0.37mS, Cut-off frequency (fT)=90.18GHz, & Gain Bandwidth product (GBW)=32.3GHz) of the proposed CP-ITSM-DLTFET is superior to almost all pre-existing Si, SiGe, & Ge based doping-less TFETs. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter has also been comprehensively studied in the paper, showing a good noise margin NMH=0.198V (39.8% of VDD) and NML=0.206V (41.2% of VDD) with a high voltage gain of 30.25 at VDD=0.5V, suggesting great potential for future low power applications

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Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

et al. 2023

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“…2(b)]. The gate oxide is deposited at a speci c angle using 45° magnetron sputtering [42][Fig. Additionally, Fig.…”

Section: Source Contact Ohimcmentioning

confidence: 99%

A High Schottky Barrier iTFET with Control Gate for Low Power Application

Lin,

Tse

2023

Preprint

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This research presents a simulated device structure for an Inductive Line Tunneling Tunnel Field-Effect Transistor (iTFET) with a high Schottky barrier and a control gate. We based our design process on real-world production components, factored in actual processing steps, and verified all software parameters to ensure the study's close alignment with practical manufacturing scenarios. Our configuration employs Silicon Germanium (SiGe), a narrow-bandgap semiconductor known for its cost-effectiveness, mature technology, and ability to enhance electron tunneling. We implemented Schottky Barrier Height (SBH) modulation engineering to increase the ON- state current (ION) by integrating an electrode into the semiconductor via Schottky contact. To further optimize the device performance, a control gate was included between the source and drain regions. This modification increased the ION and reduced the OFF-state current (IOFF) through the manipulation of the electric field. The simulation results demonstrated an average subthreshold swing (SSAVG) of 31.5 mV/dec, an ION of 4.96x10-6 A/μm, and an ION/IOFF ratio of 1.1x108 at a VDS of 0.2V, indicating a remarkably low subthreshold swing. These outcomes highlight the feasibility of utilizing a low thermal budget approach to fabricate high-performing TFETs that are well-suited for economical and low-energy applications.

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“…In this line, both homogeneous and heterogeneous tunneling junctions are proposed for TFET design. Among homogenous TFETs, the lower indirect bandgap semiconductors like-Ge 20 , Si x Ge 1-x 21,22 , Strained-Ge 23,24 , as well as lower direct bandgap semiconductors like-InAs 25 , In x Ga 1-x As 26 , Ge x Sn 1-x 27 exhibited notable improvements over the conventional Si TFET. Whereas a wide variety of semiconductor hetero-junctions are adopted for TFET design that usually incorporates heterostructure with both type-2 and type-3 band offset at the tunneling junctions.…”

Section: Performance Optimization Of Tfetsmentioning

confidence: 99%

2D materials-based nanoscale tunneling field effect transistors: current developments and future prospects

et al. 2022

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The continuously intensifying demand for high-performance and miniaturized semiconductor devices has pushed the aggressive downscaling of field-effect transistors (FETs) design. However, the detrimental short-channel effects and the fundamental limit on the sub-threshold swing (SS) in FET have led to a drastic increase in static and dynamic power consumption. The operational limit of nanoscale transistors motivates the exploration of post-CMOS devices like Tunnel FET (TFET), having steeper SS and immunity toward short channel effects. Thus the field of nanoscale 2D-TFET has gained compelling attention in recent times. The nanoscale TFET, with two-dimensional (2D) semiconductor materials, has shown a significant improvement in terms of higher on-state current and lower sub-threshold swing. In this context, the review presented here has comprehensively covered the gradual development and present state-of-arts in the field of nanoscale 2D-TFET design. The relative merits and demerits of each class of 2D materials are identified, which sheds light on the specific design challenges associated with individual 2D materials. Subsequently, the potential device/material co-optimization strategies for the development of efficient TFET designs are highlighted. Next, the experimental development in 2D-TFET design is discussed, and specific synthesis/fabrication challenges for individual material systems are indicated. Finally, an extensive comparative performance study is presented between the simulated as well as experimentally reported potential 2D materials and state-of-the-art bulk material-based TFETs.

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A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

Cited by 30 publications

References 38 publications

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

A High Schottky Barrier iTFET with Control Gate for Low Power Application

2D materials-based nanoscale tunneling field effect transistors: current developments and future prospects

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