Demonstration of non-volatile working memory through interface engineering in STT-MRAM

Yoshida, Chikako; Ochiai, Takao; Iba, Y.; Yamazaki, Yoichi; Tsunoda, Koji; Takahashi, Atsushi; Sugii, T.

doi:10.1109/vlsit.2012.6242460

Cited by 34 publications

(23 citation statements)

References 2 publications

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“…12, to evaluate the low-voltage and lowleakage operation. The detailed process of the MTJ device used in the test chip is presented in the references [2,11]. The macro size is 2.2 × 2.9 mm 2 .…”

Section: Chip Implementation and Measuremrnt Resultsmentioning

confidence: 99%

“…A spin transfer torque magnetoresistance random access memory (STT-MRAM), which stores data as magnetic resistance states, is promising for use as non-volatile memory to reduce the leakage power. It is useful as embedded memory because it can function at low voltage and because it endures over 10 16 write cycles [2]. In addition, the STT-MRAM technology makes its bitcell smaller than an SRAM so that it is suitable for use in high-density products [3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

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A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

Umeki

Yanagida

Yoshimoto

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.

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Section: Chip Implementation and Measuremrnt Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

Umeki

Yanagida

Yoshimoto

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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“…While all the nonvolatile devices described the above satisfies (2) and (3), ReRAM devices, atom switches, and PCRAM devices do not satisfy (1). In contrast, a magnetic tunnel junction (MTJ) device has virtually unlimited endurance over 10 16 [12]. However, a large amount of energy consumption for the backup operation is one major challenge for the MTJ device.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

Suzuki

Hanyu

2017

IEICE Trans. Inf. & Syst.

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SUMMARYAn energy-efficient nonvolatile FPGA with assuring highly-reliable backup operation using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 66% in comparison with that of a conventional worst-case-based approach where the long time write current pulse is used for the reliable write. key words: field-programmable gate array (FPGA), power gating, magnetic tunnel junction (MTJ) device, and low power digital

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“…A spin transfer torque magnetoresistance random access memory (STT-MRAM) is promising for use as non-volatile memory to reduce the leakage power. It is useful because it can function at low voltages and has a lifetime of over 10 16 write cycles [2]. In addition, making STT-MRAM suitable for use in high-density products [3], [4], [5], [6], [7].…”

Section: Introductionmentioning

confidence: 99%

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM

Umeki

Yanagida

Yoshimoto

et al. 2016

IPSJ Transactions on System LSI Design Methodology

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Abstract:In this paper, in order to realize 0.4 V operation of STT-MRAM, we propose the counter base read circuit. The proposed read circuit has tolerance for process variation and temperature fluctuation by changing dynamically the load curve in a time-axis at the read operation. We confirmed that the proposed read circuit can operate at the conditions of five process corners (TT, FF, FS, SF, and SS) and three temperatures (−20• C, 25• C, and 100• C) by HSPICE simulations. At the condition of TT corner and 25• C, read time of the proposed circuit is 271 ns, and energy consumption is 1.05 pJ at "1" read operation and 1.23 pJ at "0" read operation.

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Demonstration of non-volatile working memory through interface engineering in STT-MRAM

Cited by 34 publications

References 2 publications

A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM

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