Abstract:In this paper, in order to realize 0.4 V operation of STT-MRAM, we propose the counter base read circuit. The proposed read circuit has tolerance for process variation and temperature fluctuation by changing dynamically the load curve in a time-axis at the read operation. We confirmed that the proposed read circuit can operate at the conditions of five process corners (TT, FF, FS, SF, and SS) and three temperatures (−20• C, 25• C, and 100• C) by HSPICE simulations. At the condition of TT corner and 25• C, read time of the proposed circuit is 271 ns, and energy consumption is 1.05 pJ at "1" read operation and 1.23 pJ at "0" read operation.

This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line nonprecharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plateline charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.

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This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising onewrite/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46 V and access time of 140 ns. The minimum energy point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 484 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology. key words: image memory, multi-port SRAM, 8T, majority logic

This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.