Dense only phase-shift template lithography

Fritze, M.; Tyrrell, Brian; Mallen, Renee D.; Wheeler, Bruce; Rhyins, Peter D.; Martin, Patrick

doi:10.1117/12.485244

Cited by 11 publications

(7 citation statements)

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“…To include other features on the layer such as the horizontally-oriented poly-silicon connection paths and contact-landing pads, whose dimensions are not critical for cell area and can be designed larger, many * A transistor pitch, also called a "contacted pitch", is the minimum pitch between two gates with a contact between them. other template-trim approaches can be used 12,14,15,18 and the final number of exposures, masks, and resistor layers might be different. For example, since most of the gate are vertically-orientated in standard cells, it is a suitable application of Canon IDEAL method.…”

Section: Lithographic Methods For Gridded Layout Standard Cellsmentioning

confidence: 99%

“…Because there are many template-trim approaches available 12,14,15,18 for the poly-silicon layer, the final number of exposures, masks, and resistor layers might be different, leading to different impact on design rules and manufacturing cost.…”

Section: Layout Area Vs Manufacturing Costmentioning

confidence: 99%

“…The gridded layout also enables a prior fabrication and reuse of photomasks, thereby reducing manufacturing cost. 12 This makes gridded layout a very attractive option for ASIC foundries.…”

Section: Gridded Layoutmentioning

confidence: 99%

“…For example, the cost for a full 28-30 mask set for a 90 nm node is projected to be well over 1 million US dollars. 12 The high mask set cost has induced a decline recently for low volume production market, such as ASICs. A low cost process will be more likely adopted by ASIC foundries for future technology nodes.…”

Section: Two-beam Imaging and Challengesmentioning

confidence: 99%

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Performance optimization for gridded-layout standard cells

Wang

Wong²,

Lam

2004

SPIE Proceedings

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The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.

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Section: Lithographic Methods For Gridded Layout Standard Cellsmentioning

confidence: 99%

Section: Layout Area Vs Manufacturing Costmentioning

confidence: 99%

“…The gridded layout also enables a prior fabrication and reuse of photomasks, thereby reducing manufacturing cost. 12 This makes gridded layout a very attractive option for ASIC foundries.…”

Section: Gridded Layoutmentioning

confidence: 99%

Section: Two-beam Imaging and Challengesmentioning

confidence: 99%

See 2 more Smart Citations

Performance optimization for gridded-layout standard cells

Wang

Wong²,

Lam

2004

SPIE Proceedings

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“…It is pointed out [8] that full chip layouts may need to be assembled as a collection of regular printable patterns for technologies beyond 90nm, and layouts in the 65nm technology node have a high likelihood to look like regular gratings: uniform pitch and width on metal as well as polysiliconconductor (PC) layers. In [6], lithographic techniques have been demonstrated to reliably print minimum polysilicon lines which are placed on grid. In [17,15,16] Liebmann et al proposed a simplified layout optimization methodology which is based on restrictive design rules (RDRs) to better enable alternating phase shifted mask designs and control line-width on the PC layer in ultra-deep submicron technologies.…”

Section: Introductionmentioning

confidence: 99%

Technology migration technique for designs with strong RET-driven layout restrictions

Yuan

McCullen

Heng

et al. 2005

Proceedings of the 2005 International Symposium on Physical Design

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Restrictive design rules (RDRs) have been introduced as a simplified layout optimization method to better enable resolution enhancement techniques in ultra-deep submicron designs [16]. In this paper, we study the technology migration problem for designs with strong RET-driven layout restrictions, i.e., RDR constraints, which require devices (gates) to be placed on a coarse pitch and in a single orientation. In particular, we study the legalization problem with on-pitch constraints for devices with an objective of minimum layout perturbation. The problem can be formulated as an integer linear programming (ILP) problem with a set of stringent integer constraints, and it can be approximated as a mixed integer linear programming (MILP) problem. Instead of using an MILP solver to solve it, we propose a two-stage method -first the target on-pitch positions for gates are computed and second the original problem is relaxed to a linear programming problem. Library cell layouts designed in a technology with conventional ground rules have been migrated successfully to a technology with RDRs using our approach.

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Self-Assembly and Nanostructured Materials

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"Nanostructured materials" are those having properties defined by features smaller than 100 nm. This class of materials is interesting for the reasons: i) They include most materials, since a broad range of properties-from fracture strength to electrical conductivitydepend on nanometer-scale features. ii) They may offer new properties: The conductivity and stiffness of buckytubes, and the broad range of fluorescent emission of CdSe quantum dots are examples. iii) They can mix classical and quantum behaviors. iv) They offer a bridge between classical and biological branches of materials science. v) They suggest approaches to "materials-by-design". Nanomaterials can, in principle, be made using both top-down and bottom-up techniques. Self-assembly bridges these two techniques and allows materials to be designed with hierarchical order and complexity that mimics those seen in biological systems. Self-assembly of nanostructured materials holds promise as a low-cost, high-yield technique with a wide range of scientific and technological applications.

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Dense only phase-shift template lithography

Cited by 11 publications

References 0 publications

Performance optimization for gridded-layout standard cells

Performance optimization for gridded-layout standard cells

Technology migration technique for designs with strong RET-driven layout restrictions

Self-Assembly and Nanostructured Materials

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