Dependence of Electrical Characteristics on the Depth of the Recess Region in the Scaled Tantalum Nitride–Aluminum Oxide–Silicon Nitride–Silicon Oxide–Silicon Flash Memory Devices

Jang, Sang Hyun; Jin, Jun; Kim, Kyung Won; Kim, Hyun Woo; You, Joo Hyung; Lee, Keun Woo; Kim, Tae Whan

doi:10.7567/jjap.50.124202

Cited by 1 publication

(1 citation statement)

References 18 publications

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“…[3][4][5][6][7][8][9] The scaling-down of flash memory devices to achieve highstorage-density capability has been confronted with unexpected problems of the large short-channel effect, the large coupling interference, and the large leakage current. [10][11][12][13][14][15][16][17] When the gate length of the NAND flash memories scales down below 40 nm, the small coupling ratio is the critical issue because of the limitation of the floating gate (FG) and the surrounding bit lines. Investigations of the increase in the tunneling oxide thickness and the decrease in the blocking oxide thickness for the NAND flash memory devices have been performed to increase their coupling ratio.…”

Section: Introductionmentioning

confidence: 99%

Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure

Ryu

Jang

Kim

2014

Jpn. J. Appl. Phys.

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The electrical characteristics of NAND flash memories with an asymmetric interpoly-dielectric (IPD) structure and a conventional IPD structure were simulated by using a technology computer-aided sentaurus simulation tool to enhance their device performance. The floating gate potential and the on-current level of the NAND memory devices with an asymmetric IPD structure were higher than those with a conventional IPD structure. The maximum electric field formed at the rounding boundary area of the floating gate and the blocking oxide layer in an asymmetric IPD structure was 34% smaller than that in a conventional IPD structure. The trapped charges in the floating gate layer of NAND flash memories with an asymmetric IPD structure increased owing to an increase in the saturation voltage during programming and erasing operation.

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