The effects of oxide, Si wafer, and gate Al thicknesses on the substrate injection currents (J sub) of p-type metal-oxide-semiconductor structures with ultrathin oxides are studied. J sub is reported to be both trap-related ͑interface and Si bulk͒ and Si band gap-related ͑intrinsic carrier concentration͒. Both mechanisms have given rise to the stress near the Si/SiO 2 interface. Current-voltage and capacitance-voltage characterizations reveal that J sub increases with oxide thickness, which is suggested to be dominated by the trap-related mechanism. A stronger dependence of J sub on a change in oxide thickness is observed for a thicker Si wafer, which is proposed to be mainly caused by the band gap-related mechanism. Furthermore, a thicker gate Al introduces a higher J sub , which is proposed to be due to both the trap-related and the band gap-related mechanisms.