We demonstratehigh-performance self-aligned In 0.53 Ga 0.47 As-channel MOSFETs with effective channel length L EFF down to 20 nm, peak transconductance G MSAT over 2200 μS/μm at L EFF = 30 nm and supply voltage V DD = 0.5 V, thin inversion oxide thickness T INV = 1.8 nm, and low series resistance R EXT = 270 Ω.μm. These MOSFETs operate within 20% of the ballistic limit for L EFF ≤ 30 nm and are among the best In 0.53 Ga 0.47 As FETs in literature. We investigate the effects of channel/barrier doping on FET performance and show that increase in mobility beyond ~ 500 cm 2 /Vs has progressively smaller impact as L EFF is scaled down. Our self-aligned MOSFETs were fabricated using a CMOS-compatible process flow that includes gate and spacer formation using RIE, source/drain extension (SDE) implantation, and in-situ-doped raised source/drain (RSD) epitaxy. This process flow is manufacturable and easily extendable to non-planar architectures.
I. INTRODUCTIONMany III-V materials have significantly better electron transport properties than Si, and therefore, have been actively investigated as the NFET solution for high-performance CMOS applications [1]. While most III-V research has been focused on HEMTs [2]-[18] or MOS-HEMTs [19]-[32], very few works have focused on MOSFETs [33]-[39]. MOSFETs are required for high performance and device density scaling because MOS-HEMTs have high overlap capacitance while HEMTs have large foot-print and high gate leakage [36]. Therefore, we have focused on self-aligned MOSFETs and processes that are not only manufacturable but also compatible with CMOS applications [36]. In this work, we demonstrate high-performance self-aligned In 0.53 Ga 0.47 As MOSFETs with L EFF down to 20 nm and peak G MSAT over 2200 μS/μm at V DD = 0.5 V. This work presents 2× higher performance compared to [36], and our devices are among the best In 0.53 Ga 0.47 As FETs in literature.
