Deposited inter-polysilicon dielectrics for nonvolatile memories

Abstract

Deposited instead of thermally grown oxides were studied to form very high-quality inter-polysilicon dielectric layers for embedded nonvolatile memory application. It was found that by optimizing the microstructure, i.e., texture and morphology of the polysilicon layers, and by optimizing the post dielectric deposition anneal, very high-quality dielectric layers can be obtained. In this paper it is shown on simple capacitor structure level and full EEPROM device level that the electrical properties of interpoly dielectric layers can be improved tremendously by using deposited dielectric layers with additional rapid thermal anneal. Typical results are: a high charge-to-breakdown (QBD 25 C/cm 2 ); low leakage currents and decreased charge trapping during constant current stress. An additional advantage is the low thermal budget, which is very attractive for embedded applications. However, results depend on the polysilicon preparation, dielectric type and RTP anneal environment.From electrical evaluation it appeared that even for deposited dielectric layers the influence of polysilicon surface roughness and corners is considerable.The optimized combination of flat polysilicon layers, deposited inter-polysilicon dielectric and additional optimized rapid thermal anneal have been applied in full EEPROM devices. Cycling over one million cycles was possible, which indicates an endurance improvement by a factor of 10.

Mesoscale Confinement Effects and Emergent Quantum Interference in Titania Antidot Thin Films

“…Thus, it is not immediately obvious how percolation could be occurring in the antidot films, and we investigated competing mechanisms that could explain the anomalous conductivity. See the Supporting Information for analysis that excludes a space-charge-limited current, a Schottky barrier, a trap-filled limit current, Fowler–Nordheim tunneling and the Poole–Frenkel effect, and capacitor breakdown. − …”

High quality Al/sub 2/O/sub 3/ IPD with NH/sub 3/ surface nitridation

“…The roughness of the bottom interface with and without surface nitridation are 2.76 nm and 3.32 nm, respectively, after selective IPD removal. Smoother interface is helpful in reducing the localized field and, hence, leads to lower leakage current and higher breakdown field [3], [6], [7]. The origin of the resultant smoother interface is hypothesized to be closely related to the capability of Si-N layer in blocking oxygen diffusion during post-deposition O annealing, as is evidenced by the high frequency -measurements and Auger electron spectra (AES).…”

Reliability of HTO based high-voltage gate stacks for flash memories

“…Because the high-voltage gate oxide is not thermally grown, the critical influence of a high-temperature thermal oxidation on the STI regions and diffusions is eliminated. Nevertheless, reliability issues, such a electron trapping in HTO were reported to be a limitation [2] and special anneals in N 2 O were proposed to improve the HTO properties.…”