Design, analysis and performance comparison of GNRFET based 8-bit ALUs

Aradhya, H. V. Ravish; Madan, H R; Suraj, M S; Mahadikar, Megaraj T; Muniraj, R.; Moiz, Mohammed; Bharadwaj, Abhijith

doi:10.1109/rains.2016.7764366

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…Due to the extreme dimensions of graphene nano ribbons we can assume that they would include a small number of dimer lines (5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20). Additionally we can assume that the ribbons will be in Armchair GNR configuration (AGNR) [10].…”

Section: A Physical Propertiesmentioning

confidence: 99%

“…Second by using these devices and the GNRFET models available in literature we are simulating analog mixed signal blocks and estimating their performances. The existing GNRFET circuits are mainly digital designs [6,7] however in our work we chose to study frequently used analog mixed signal circuit blocks such as telescopic amplifier and comparators. Additionally the same circuit blocks are designed using 14nm Silicon CMOS transistors.…”

Section: Introductionmentioning

confidence: 99%

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Desinging Analog Mixed Signal Circuits Using Graphene Nano Ribbon Field Effect Transistors

Karalar

2020

Balkan Journal of Electrical and Computer Engineering

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Graphene is a 2D material formed by planar honeycomb placement of Carbon atoms. Besides its many superior physical properties it has superior electronic properties foremost of which is the high mobility it possesses. Due to this high mobility many Graphene based transistors have been designed. Graphene nano ribbons exhibit a band gap property, which is crucial for implementing transistors as switches. Moreover there exist models for these Graphene Nano Ribbon devices. In this work we first propose a gate array based manufacturing approach. Next assuming devices manufactured in this gate array methodology. We realize and simulate analog mixed signal blocks using Graphene Nano Ribbon transistors. The particular blocks that we used included telescopic amplifiers and StrongARM latches. Next we compared these blocks' performances against the same blocks implemented in 14nm high performance Silicon CMOS transistors. As a result we observed that the graphene transistors could attain comparable performances to circuits designed in 14nm CMOS. Specifically Graphene blocks can reach up to 80% of the bandwidth of Silicon devices. However Graphene devices have greater power consumption as a result of higher leakage current.

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Section: A Physical Propertiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Desinging Analog Mixed Signal Circuits Using Graphene Nano Ribbon Field Effect Transistors

Karalar

2020

Balkan Journal of Electrical and Computer Engineering

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“…Among these adders, 100nm Graphene Barristors was proven to have the best performance. Aradhya et al [13] conducted research in 2016 which presented the design of 10 nm CMOS and GNRFET based 8-bit ALU architecture. These ALUs were simulated using HSPICE and compared.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Johari

Tan²,

Rasol³

et al. 2022

Elektrika

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Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.

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Design of ternary logic gates and circuits using GNRFETs

Madhuri

Sunithamani

2020

IET Circuits, Devices & Systems

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Design, analysis and performance comparison of GNRFET based 8-bit ALUs

Cited by 4 publications

References 9 publications

Desinging Analog Mixed Signal Circuits Using Graphene Nano Ribbon Field Effect Transistors

Desinging Analog Mixed Signal Circuits Using Graphene Nano Ribbon Field Effect Transistors

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Design of ternary logic gates and circuits using GNRFETs

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