Design and analysis of 3D IC-based low power stereo matching processors

Ok, Seung-Ho; Bae, Kyeong-ryeol; Lim, Sung Kyu; Moon, Byungin

doi:10.1109/islped.2013.6629260

Cited by 3 publications

(2 citation statements)

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“…In addition, we expand our previous work [15] to investigate the impact of technology process scaling (130 nm down to 45 nm) and TSV scaling (2.2 μm down to 0.8 μm) on the power and area benefits of 3D stacking. We design our 3D-stacked stereo matching processors using GlobalFoundries 130 nm and Nangate 45 nm process design kits (PDKs) and compare them with their 2D IC counterparts regarding power consumption and wire length.…”

Section: Introductionmentioning

confidence: 99%

“…In contrast to the goals of the work mentioned above [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 ], one of the primary goals of this research is to analyze the influence of reduced wire length that results from vertical stacking on power consumption by comparing 3D ICs with their 2D IC counterparts. In addition, we expand our previous work [ 15 ] to investigate the impact of technology process scaling (130 nm down to 45 nm) and TSV scaling (2.2 μm down to 0.8 μm) on the power and area benefits of 3D stacking. We design our 3D-stacked stereo matching processors using GlobalFoundries 130 nm and Nangate 45 nm process design kits (PDKs) and compare them with their 2D IC counterparts regarding power consumption and wire length.…”

Section: Introductionmentioning

confidence: 99%

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The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

Lee

Shim

et al. 2017

Sensors

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Abstract:Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

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Section: Introductionmentioning

confidence: 99%