Design and Analysis of a Low Loss, Wideband Digital Step Attenuator With Minimized Amplitude and Phase Variations

Song, Ickhyun; Cho, Moon-Kyu; Cressler, John D.

doi:10.1109/jssc.2018.2827934

Cited by 65 publications

(28 citation statements)

References 25 publications

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“…PERFORMANCE BENCHMARKING TABLE II represents the performance summary of our attenuator and the similar studies reported in the literature. The attenuators described in [5], [8], [9], and [13] have less bit resolution than our attenuator and exploit the benefits of using smaller technology nodes featuring devices with lower R on and parasitic capacitors, which provide a significant advantage in performance as mentioned earlier. Moreover, [8] and [9] both suffer in terms of RLs and [8] has only 11 dB of attenuation range with a low IP 1dB of 5 dBm.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

A 7-Bit Reverse-Saturated SiGe HBT Discrete Gain Step Attenuator

Davulcu

Burak

Gürbüz

2020

IEEE Trans. Circuits Syst. II

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In this study, the analysis, design and measured results of a fully integrated 7-Bit step attenuator implemented in a 0.25-µm Silicon-Germanium (SiGe) BiCMOS process technology, are described. The attenuator is designed based on delicately ordered and cascaded Π/T type attenuation blocks, which are comprised of series/shunt switches employing SiGe hetero-junction bipolar transistors (HBTs) with peak fT /fmax of 110/180 GHz. HBTs are employed as a series switch to decrease the insertion-loss of the attenuator. Moreover, to authors' best knowledge, this is the first study presenting the effect of employing reverse-saturated HBTs as a shunt switch for each attenuation blocks. Thanks to this advancement, the highest input-referred 1-dB compression point (IP 1dB ) is reported for Si-based similar studies. This method also decreases the insertion-loss of the proposed attenuator. The measurements result in the state-ofthe-art performance with 28.575 dB attenuation range by 0.225 dB gain steps while maintaining 7-bit amplitude resolution across 6.6 GHz to 12.8 GHz frequency band, where RMS phase error remains below 3.3 • and insertion loss (IL) is less than 12.4 dB. The measured IP 1dB of the attenuator is 13.5 dBm while drawing 8 mA from 3.3 V supply. The die occupies an area of 1.37 mm x 0.56 mm excluding pads.

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Section: Simulation and Measurement Resultsmentioning

confidence: 99%

A 7-Bit Reverse-Saturated SiGe HBT Discrete Gain Step Attenuator

Davulcu

Burak

Gürbüz

2020

IEEE Trans. Circuits Syst. II

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“…Finally, 4.0-dB and 8.0-dB attenuator cells are designed with the structure shown in Figure 2c, where a capacitor, CP2, is connected in parallel with RP2. This not only reduces the phase imbalance but also prevents the bandwidth reduction occurring in high attenuation cells [16][17][18]. Figure 3 shows a full schematic and micrograph of the 5-bit digital attenuator.…”

Section: -Bit Digital Attenuatormentioning

confidence: 99%

A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset

et al. 2020

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This paper presents a Ku-band monolithic multifunction transmitter and receiver chipset fabricated in 0.25-μm GaAs pseudomorphic high-electron mobility transistor technology. The chipset achieves a high level of integration, including a 4-bit 360° digital phase shifter, 5-bit 15.5-dB digital attenuator, amplifier and 9-bit digital serial-to-parallel converter for digital circuit control. Since the multifunction chipset includes a medium power amplifier and a low-noise amplifier, it features high P1dB and low noise figures over the full Ku-band frequencies. The multifunction transmitter shows a peak gain of 16.5 dB with output P1dB of 19.2 dBm at 15 GHz. The multifunction receiver shows a peak gain of 17.3 dB with noise figure of 2.5 dB at 15 GHz. The attenuation range is 15.5 dB with a step of 0.5 dB and the phase shift range is 360° with a step of 22.5°. Each chip area of the transmitter and receiver is 4.2 × 2.8 mm2.

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“…Traditional capacitance C c and C p compensation correction networks are widely used in the digital control step attenuator circuit [18,20,21], but there are large insertion losses, especially in large 8 and 16 dB attenuation units. In order to solve this problem, a parallel capacitor C p is added to the attenuation shunt branch in 8 and 16 dB attenuation cells.…”

Section: Proposed Circuit Design and Analysismentioning

confidence: 99%

“…This work is compared with other recently published similar digital control step attenuators in Table 3. The proposed 6-bit digital control step attenuator has better insertion loss compared with [16][17][18] and the higher IP -1dB than [13,16,21]. Compared with [12,13,17], this design has wide frequency coverage.…”

Section: Comparison With Relevant Digital Control Step Attenuatorsmentioning

confidence: 99%

“…A variety of passive attenuator circuits have been designed in [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24]. There are three most-used topologies in the passive attenuators: Switched path attenuators [6][7][8][9], distributed attenuators [10,11] and switched T/Pi attenuators [12][13][14][15][16][17][18][19][20][21][22][23][24]. Switched path attenuators topology use single-pole-double-throw (SPDT) switches to control the signal between reference thru line path and the resistive attenuation network path.…”

Section: Introductionmentioning

confidence: 99%

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A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

Luo

Yao

et al. 2019

Electronics

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A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46° in the 12–17 GHz frequency range. The total chip area is 1 × 0.9 mm2.

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Design and Analysis of a Low Loss, Wideband Digital Step Attenuator With Minimized Amplitude and Phase Variations

Cited by 65 publications

References 25 publications

A 7-Bit Reverse-Saturated SiGe HBT Discrete Gain Step Attenuator

A 7-Bit Reverse-Saturated SiGe HBT Discrete Gain Step Attenuator

A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset

A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

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