Design and Analysis of an Approximate Adder with Hybrid Error Reduction

Abstract

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation

“…The lower-part OR adder (LOA) and error tolerant adder I (ETAI) are two representative approximate adders implemented using an approximate FA for the least significant bits (LSBs) of a multibit adder [13], [19], and many of their variants were presented so far [14]- [18], [20], [21].…”

“…Finally, Section VI concludes the work. [18]. A n-1:n-k B n-1:n-k S n-1:n-k FIGURE 2: Block diagram of SETA [21].…”

An Approximate GEMM Unit for Energy-Efficient Object Detection

“…Approximate computing is a new paradigm where an acceptable error is induced in the computing to achieve more energy-efficient processing [ 28 , 29 , 30 , 31 , 32 , 33 ]. It has been introduced at different system levels [ 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 ], and a large number of approximate arithmetic circuits have been designed to save chip area and energy [ 35 , 38 , 46 , 47 , 48 , 49 , 50 , 51 ]. Multiplication is a very common, but expensive operation, with exact multipliers being large circuits that consume a significant amount of energy.…”

Approximate adder design with simplified lower-part approximation

“…Computationally intensive applications, such as image processing, machine learning, and data mining, may have inherent error tolerance, and a certain amount of computation error is acceptable in these applications [2,3,4,5,6]. Therefore, the design of efficient approximate adders that reduce power and energy has drawn great attention, and a large number of approximate adders have been proposed in the recent years [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29]. The lower-part OR adder (LOA) divides an adder into two: accurate and inaccurate parts [7].…”

“…Hence, a couple of ETAI variants that include a carry prediction technique to improve the accuracy were proposed in [10,11]. The ETAI sequentially checks the input bits from the most significant bit (MSB) position to the LSB; therefore, the delay of the inaccurate part is a bit longer than that of the LOA and its variants [7,8,12]. In other words, the critical path delay will likely exist in the inaccurate part when its size is larger than the accurate part, resulting in overall speed degradation and poor energy efficiency.…”