Design and analysis of digital data recovery circuits using oversampling

Jou, Shyh-Jye; Lin, Chih-Hsien; Chen, Yen-Hung; Li, Zhenghong

doi:10.1049/iet-cds:20045173

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…This is benefit in case of measuring very low bit error rates (10 -9 and lower) as the jitter measurement time is negligible compared to time required to measure BER using a standard BER measurement devices [8]. The jitter is also often used to characterize properties of transmitters (jitter generation) and receivers (jitter tolerance) [6], [7].…”

Section: Introductionmentioning

confidence: 99%

In-system jitter measurement using FPGA

Kubíček

2010

20th International Conference Radioelektronika 2010

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The paper describes architecture, detailed implementation and measurement results of newly developed jitter measurement device. The device is implemented using a single FPGA. Probably the biggest benefit of the proposed method is that it requires no external components, just the FPGA. As such it can be implemented into an existing receiver with an FPGA without any changes to its hardware.The new jitter measurement block was implementer and tested on a real link. Comparison with jitter measurement using an oscilloscope is given to prove its reasonable performance. Compared to previously published jitter measurement methods the module is able to monitor high frequency jitter. It is also very efficient in terms of required hardware resources.

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Section: Introductionmentioning

confidence: 99%

In-system jitter measurement using FPGA

Kubíček

2010

20th International Conference Radioelektronika 2010

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“…8. show an all-digital data recovery circuit [7] and a decoder. The oversampling based multi-phase sampler samples five point in a bit time, so a frequency divider divides the 10-MHz clock to 40 250-kHz multi-phase clocks and a 2-MHz clock for sampler and decoder respectively.…”

Section: All-digital Data Recovery Circuitmentioning

confidence: 99%

A 80-uW 2-Mb/s transceiver for human body channel binaural communication

Sun

Chen

Shen

et al. 2012

2012 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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We use a body channel and a low-power transceiver design to achieve binaural communication for hearing aids. The measured bandwidth of the body channel is 1 MHz to 7.5 MHz. The transmitter encodes and transmits data of 2-Mb/s and 1-V peak-to-peak square waveform to the electrodes connected to the body. The receiver includes an analog front end (AFE), an all-digital data recovery circuit and a decoder. This chip is implemented with a 65-nm CMOS process using 0.5-V supply in the digital transceiver and 1-V supply in the AFE. When working at 2 Mb/s, the power consumption is only 80 uW.

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“…Jitter is defined as the deviation of a signal's transition point from its ideal position in time [13], thus the period of the signal varies from its nominal period. The effect of jitter on the edge of a clock signal is shown in Fig.…”

Section: Jittermentioning

confidence: 99%

A 2-5 Gbps fully differential 3X oversampling CDR for high-speed serial data link

Kiddinapillai¹

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Design and analysis of digital data recovery circuits using oversampling

Cited by 9 publications

References 13 publications

In-system jitter measurement using FPGA

In-system jitter measurement using FPGA

A 80-uW 2-Mb/s transceiver for human body channel binaural communication

A 2-5 Gbps fully differential 3X oversampling CDR for high-speed serial data link

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