Design and analysis of MoS&lt;inf&gt;2&lt;/inf&gt;-based MOSFETs for ultra-low-leakage dynamic memory applications

Kshirsagar, Chaitanya; Xu, Weichao; Kim, Chris H.; Koester, Steven J.

doi:10.1109/drc.2014.6872360

72nd Device Research Conference 2014

DOI: 10.1109/drc.2014.6872360

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Design and analysis of MoS<inf>2</inf>-based MOSFETs for ultra-low-leakage dynamic memory applications

Chaitanya Kshirsagar

Weichao Xu

Chris H. Kim

et al.

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Cited by 7 publications

(8 citation statements)

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“…Comparison of the theoretical predictions 29 for MoS 2 with experimental results 32 for silicon suggest that two orders-ofmagnitude reduction in refresh power could be possible at fixed cell size using MoS 2 .…”

mentioning

confidence: 88%

“…28 For these reasons, combined with its potential for monolayer thickness, short channel effects (SCEs) and gate-induced drain leakage (GIDL) are expected to be substantially suppressed in MoS 2 compared to silicon and many of the narrower-gap TMDs, making MoS 2 suitable for extremely low leakage static and dynamic memories. 29 In memory applications, particularly dynamic memories, the MOSFET leakage requirements can be quite different from those in logic circuits. In the latter, the most important figure of merit is the subthreshold slope, SS, which ensures the lowest possible off-state current (at zero gate bias) while still maintaining acceptable drive current.…”

mentioning

confidence: 99%

“…31−34 Therefore, for many memory applications, it is the minimum current, I MIN , rather that SS, that is the most important figure of merit for low-power operation. Furthermore, since dynamic random access memory (DRAM) power is dominated by the refresh process, and due to the fact that the refresh rate is proportional to I MIN , 29 then the total power consumption should also decrease in proportion to I MIN , provided that all other memory parameters remain the same.…”

mentioning

confidence: 99%

“…Silicon has narrower band gap of E g = 1.1 eV and tunneling-relevant m * ∼ 0.2 m 0 . For these reasons, combined with its potential for monolayer thickness, short channel effects (SCEs) and gate-induced drain leakage (GIDL) are expected to be substantially suppressed in MoS 2 compared to silicon and many of the narrower-gap TMDs, making MoS 2 suitable for extremely low leakage static and dynamic memories …”

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confidence: 99%

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Dynamic Memory Cells Using MoS₂ Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Kshirsagar

et al. 2016

ACS Nano

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Two-dimensional semiconductors such as transition-metal dichalcogenides (TMDs) are of tremendous interest for scaled logic and memory applications. One of the most promising TMDs for scaled transistors is molybdenum disulfide (MoS2), and several recent reports have shown excellent performance and scalability for MoS2 MOSFETs. An often overlooked feature of MoS2 is that its wide band gap (1.8 eV in monolayer) and high effective masses should lead to extremely low off-state leakage currents. These features could be extremely important for dynamic memory applications where the refresh rate is the primary factor affecting the power consumption. Theoretical predictions suggest that leakage currents in the 10(-18) to 10(-15) A/μm range could be possible, even in scaled transistor geometries. Here, we demonstrate the operation of one- and two-transistor dynamic memory circuits using MoS2 MOSFETs. We characterize the retention times in these circuits and show that the two-transistor memory cell reveals MoS2 MOSFETs leakage currents as low as 1.7 × 10(-15) A/μm, a value that is below the noise floor of conventional DC measurements. These results have important implications for the future use of MoS2 MOSFETs in low-power circuit applications.

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confidence: 88%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Dynamic Memory Cells Using MoS₂ Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Kshirsagar

et al. 2016

ACS Nano

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“…MoS 2 , WSe 2 , etc) 7 8 9 10 11 have an advantage for suppressing the source-to-drain tunneling current in ultra-scaled transistors and offers superior immunity to short-channel effects 12 . However, these semiconductors have relatively high effective mass and theoretical predication suggests that MX 2 FETs may be better suited for low-power applications rather than high performance logic 13 .…”

mentioning

confidence: 99%

Black Phosphorus Based Field Effect Transistors with Simultaneously Achieved Near Ideal Subthreshold Swing and High Hole Mobility at Room Temperature

Liu¹,

Ang

Wang

et al. 2016

Sci Rep

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Black phosphorus (BP) has emerged as a promising two-dimensional (2D) material for next generation transistor applications due to its superior carrier transport properties. Among other issues, achieving reduced subthreshold swing and enhanced hole mobility simultaneously remains a challenge which requires careful optimization of the BP/gate oxide interface. Here, we report the realization of high performance BP transistors integrated with HfO2 high-k gate dielectric using a low temperature CMOS process. The fabricated devices were shown to demonstrate a near ideal subthreshold swing (SS) of ~69 mV/dec and a room temperature hole mobility of exceeding >400 cm2/Vs. These figure-of-merits are benchmarked to be the best-of-its-kind, which outperform previously reported BP transistors realized on traditional SiO2 gate dielectric. X-ray photoelectron spectroscopy (XPS) analysis further reveals the evidence of a more chemically stable BP when formed on HfO2 high-k as opposed to SiO2, which gives rise to a better interface quality that accounts for the SS and hole mobility improvement. These results unveil the potential of black phosphorus as an emerging channel material for future nanoelectronic device applications.

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Circuit‐Level Memory Technologies and Applications based on 2D Materials

Liu

Yang

et al. 2022

Advanced Materials

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random-access memory (DRAMs), static random-access memory (SRAMs), [1] and flash memory, [2] multiple transistors and capacitors are employed to constitute a single functional cell. These functional cells are typically integrated to form a memory array for advanced functionality, miniaturized footprints, low power consumption, and reduced latency. Traditional silicon-based complementary metal-oxidesemiconductor (CMOS) technology has been widely used to build these memory arrays. However, the performance improvement of CMOS-based memory relies on the advance of nanofabrication technology to scale down the feature size of transistors, which is approaching the physical limit. [3] To overcome this bottleneck, emerging memory technologies are brought up as promising supplements to conventional memory devices. [4] These novel types of memory include resistive random-access memory (RRAM), [5,6] ferroelectric RAM (FeRAM), [7] optoelectronic RRAM (ORRAM), [8,9] phase-change memory (PCM), [10] and spin-transfer torque magnetoresistive RAM (STT-MRAM). [11,12] Furthermore, emerging memory devices allow non-von-Neumann architectures that pave the way toward high-performance in-memory computing technology. [13,14] For example, memristive crossbar arrays composed of 1-transistor-1-resistor (1T1R) unit cells can enable in-memory computing and are the most cost-efficient thanks to their two-terminal structure. [15] Advanced 3D monolithic stacking integration also emerges as a promising approach to Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

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Design and analysis of MoS<inf>2</inf>-based MOSFETs for ultra-low-leakage dynamic memory applications

Cited by 7 publications

References 5 publications

Dynamic Memory Cells Using MoS₂ Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Dynamic Memory Cells Using MoS₂ Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Black Phosphorus Based Field Effect Transistors with Simultaneously Achieved Near Ideal Subthreshold Swing and High Hole Mobility at Room Temperature

Circuit‐Level Memory Technologies and Applications based on 2D Materials

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Design and analysis of MoS<inf>2</inf>-based MOSFETs for ultra-low-leakage dynamic memory applications

Cited by 7 publications

References 5 publications

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Black Phosphorus Based Field Effect Transistors with Simultaneously Achieved Near Ideal Subthreshold Swing and High Hole Mobility at Room Temperature

Circuit‐Level Memory Technologies and Applications based on 2D Materials

Contact Info

Product

Resources

About

Dynamic Memory Cells Using MoS₂ Field-Effect Transistors Demonstrating Femtoampere Leakage Currents

Dynamic Memory Cells Using MoS₂ Field-Effect Transistors Demonstrating Femtoampere Leakage Currents