Design and Application of Power Optimized High-Speed CMOS Frequency Dividers

A dynamic current mode design approach of 2/3 prescaler for phase locked loop application

“…The literature have witnessed many different efforts of designing prescaler circuits. To operate in higher frequency range, a technique was proposed in [1] using fundamental CMOS; but it consumes larger die area [2]. A multiphase quasi-differential technique was employed in [3] to attain a better trade-off exist between the power and speed.…”

“…Low power and high frequency operation play an important role in modern communication circuit, where frequency translation or prescaler device is broadly used in the design of phase-locked loops (PLLs) and clock and data recovery modules. There have been various techniques to design a prescaler circuit such as current mode logic (CML), dynamic logic divider, TSPC and ILFD, which operates at higher input frequency with wider range [1][2][3]. However, the design of divide-by-2/3 at higher input frequency is a tough task.…”

A novel clock generation algorithm for system-on-chip based on least common multiple

“…One of the most effective ways to generate many frequencies from a single frequency without using a PLL is by integer division. This is because, in integrated circuits, accurate clock divider circuits can be designed using counters made of flip flops [16,17]. Given S and S m , the problem is to find a set of frequencies S 0 such that they can be generated from a single clock frequency, f h by integer division.…”

A 28 GHz Static CML Frequency Divider with Back-Gate Tuning on 22-nm CMOS FD-SOI Technology

“…Dynamic dividers are low power and narrowband while static can be made more broadband at the cost of power and small speed penalty [2]. Advantage of static frequency dividers is that some variants can provide differential I/Q phases, which can be used in (de)modulation, for example [3]. Especially in mmWave circuits, broadband I/Q phase generation is valuable feature because passive alternatives such as poly-phase filters are very lossy and require power hungry buffers in the inputs and outputs [4].…”