Design and Comparison of Multiplier using Vedic Sutras

Lad, Shraddha; Bendre, Varsha

doi:10.1109/iccubea47591.2019.9128517

Cited by 17 publications

(3 citation statements)

References 8 publications

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“…Future work will focus on increasing instructions and creating a pipelined design with less clock cycles per instruction. Shradda Lad et al [5] presented in this paper about a highly efficient Vedic multiplier unit using various Sutras of Vedic Mathematics. The design, synthesis, and simulation of a 16-bit Vedic multiplier unit were performed using Vivado 17.1 and Verilog.…”

Section: IImentioning

confidence: 99%

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Sai,

Vinay,

Tharun

et al. 2024

IJRASET

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In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

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Section: IImentioning

confidence: 99%

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Sai,

Vinay,

Tharun

et al. 2024

IJRASET

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“…However, FPGA implementation of a complex multiplier has not been discussed. Further, path delay analysis of Vedic real multiplier architectures, which will enable to choose architecture with minimum delay [12].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

et al. 2023

IJFMR

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: Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. This paper presents, Design and Implementation of FPGA based Complex Floating Point Multiplier using Combined Integer and Floating point Multiplier (CIFM). The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The architectures for the three multiplier solutions of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6 and their performance is compared. The complex floating point multiplication with single precision using CIFM multiplier has comparatively less amount of delay and power consumption with respect to Vedic and Array multiplier.

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“…Kamble and Ugalehave compared various multipliers and concluded that Wallace tree algorithm with Booth recoder is recommended for fast computations with drawback of larger area whereas select shift and add multiplication algorithm can be used for chips having less area [5]. Various Vedic multipliers are analyzed for the performance parameters like delay, power and area by the authors, Lad and Bendre [6]. The authors concluded that Ekadhikena Purvena sutra can reduce the area by 70.26% and increase the speed by 90.41% compared to Urdhwa Tiryakbhyam sutra and Nikhilam sutra gives optimum results in term of area, delay and power.…”

Section: Introductionmentioning

confidence: 99%