Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

Supply chains for 3D IC integration manufacturing

“…All these steps should be done by the OSAT. Separately, the memory wafer is subjected to either micro bumping with tiny solder bumps, for example [16] or Cupillars with solder caps, for example [17]. Then the wafer is diced into individual chips with micro bumps/Cu-pillars.…”

Effects of Low-k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

“…[6][7][8][9][10] Moreover, the porous SiOCH film has low modulus and weak adhesive strength with SiCN cap film, degrading reliability in chip packaging interaction (CPI). [11][12][13][14][15][16] In order to prevent such degradations of interconnect performances, SiO 2 hard mask (HM), etch stop layer (ES), and the hybrid structure with porous low-k materials as the IMD films and rigid low-k materials as the ILD films have been investigated. [6][7][8][9][10][17][18][19][20][21][22][23] However, the introduction of such higher-k materials causes the increase of effective k-value (k eff ), which is derived from comparison between measured C int and calculated C int by assuming the uniform k eff material for all dielectrics such as IMD, ILD, hard mask (HM), and cap layer.…”