Design and Evaluation of a CMOS Image Sensor with Dual-CDS and Column-parallel SS-ADCs

Abstract

Abstract-This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a fieldprogrammable gate array (FPGA) integrated module. The CIS is composed of a 320 x 240 pixel array with 3.2 μm x 3.2 μm pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a 0.11-μm CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

Design of Low-Noise CMOS Image Sensor Using a Hybrid-Correlated Multiple Sampling Technique

“…In general, CIS uses a correlated double sampling (CDS) technique to reduce readout noise by sampling the output voltages of the pixel twice. A correlated multiple sampling (CMS) technique that repeats the CDS process several times has been proposed to reduce DRN [7][8][9][10]. Figure 1a,b show the analog-to-digital converter (ADC) conversion periods during signal sampling when using CDS and CMS, respectively.…”

Low‐power column counter with a logical‐shift algorithm for CMOS image sensors

“…Introduction: CMOS image sensors (CIS) that consist of columnparallel single-slope ADCs (SS-ADC) are widely used for mobile applications because of their simple structure and good linearity [1,2]. To minimise the variety of noise sources from pixels and read-out circuits (such as flicker noise, fixed-pattern noise etc.…”