Abstract-This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a fieldprogrammable gate array (FPGA) integrated module. The CIS is composed of a 320 x 240 pixel array with 3.2 μm x 3.2 μm pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a 0.11-μm CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

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