Design and high-speed test of (4 × 8)-bit single-flux-quantum shift register files

Fujiwara, K.; Yamashiro, Y.; Yoshikawa, Nobuyuki; Fujimaki, Akira; Terai, Hirotaka; Yorozu, Shinichi

doi:10.1088/0953-2048/16/12/030

Cited by 12 publications

(9 citation statements)

References 10 publications

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“…The most successful superconducting memory to date is a 4-kbit RAM using vortex transitional memory cells and Josephson latching gates [2]. An SFQ RAM composed of an SFQ shift register array is under investigation, but its circuit scale is still small [3].…”

Section: Introductionmentioning

confidence: 99%

Characterization of 4 K CMOS Devices and Circuits for Hybrid Josephson-CMOS Systems

Yoshikawa

Tomida

Tokuda

et al. 2005

IEEE Trans. Appl. Supercond.

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Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 m, 0.25 m, and 0.35 m commercial CMOS processes. Their static I-V characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured by using ring oscillators agree well with the simulation results. The experimental results indicate about 40% speedup from 300 K to 4.2 K. A three-transistor DRAM cell for a Josephson-CMOS hybrid memory is also investigated at low temperature. The temperature dependence of the retention time shows an exponential increase at low temperatures. Based on the lowtemperature CMOS device model, we have developed short-delay CMOS amplifiers, which would amplify a 40 mV voltage input to CMOS voltage level with the propagation delay of about 100 ps, assuming the use of a 0.18 m CMOS process. We have measured the propagation delay of the CMOS amplifier by using a single-flux-quantum (SFQ) delay measurement system. This is a complete demonstration of the signal exchanges between SFQ and CMOS circuits at 4.2 K.

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Section: Introductionmentioning

confidence: 99%

Characterization of 4 K CMOS Devices and Circuits for Hybrid Josephson-CMOS Systems

Yoshikawa

Tomida

Tokuda

et al. 2005

IEEE Trans. Appl. Supercond.

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“…We evaluate the area and power consumption on the basis of the number of JJs. In this evaluation, we regard an SFQ shift register memory presented in [36] as a traditional bit-serial cache explained in Fig. 4 (b) because of the lack of comparable design information for SFQ bit-serial caches, and we use it as a baseline.…”

Section: Methodsmentioning

confidence: 99%

“…The dynamic power is estimated by assuming the worst case, i.e., the switching activity α is 1.0, whereas the static power is obtained by multiplying the average leakage power of a JJ and the total number of JJs requiblack to implement the cache. On the basis of the design report [36], we assume that the area of one JJ is 8.69 × 10 −4 mm 2 , and the access latency and area of the baseline are 1,333 ps and 265.9mm 2 , respectively.…”

Section: Methodsmentioning

confidence: 99%

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing

Ishida

Tanaka

Ono

et al. 2018

IEICE Trans. Electron.

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SUMMARYCMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.

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“…The microprocessor was operated at 18 GHz, and the experimentally demonstrated maximum performance was 240 MIPS [8]. We also demonstrated the operation of a further improved version, called , at 21 GHz, which was integrated with a 4-byte SFQ memory [9].…”

Section: Introductionmentioning

confidence: 98%

Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$

Yamanashi

Tanaka

Akimoto

et al. 2007

IEEE Trans. Appl. Supercond.

100

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A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1 , was designed and tested. The CORE1 has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1 8, have been implemented using the CONNECT cell library and the SRL 2.5 kA cm 2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1 8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1 8 microprocessors by on-chip high-speed tests.

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Design and high-speed test of (4 × 8)-bit single-flux-quantum shift register files

Cited by 12 publications

References 10 publications

Characterization of 4 K CMOS Devices and Circuits for Hybrid Josephson-CMOS Systems

Characterization of 4 K CMOS Devices and Circuits for Hybrid Josephson-CMOS Systems

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing

Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, ${\rm CORE}1\beta$

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