Design and implementation computing unit for laser jamming system using spatial parallelism on FPGA

Yousif, Omar F.; Salih, Muataz H.; Hassnawi, L. A.; Albreem, Mahmoud A.; Seddeq, Mays Q.; Isam, Hiba M.

doi:10.1109/icsipa.2015.7412160

Cited by 2 publications

(3 citation statements)

References 5 publications

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“…The Altera FLEX FPGA family utility was used in [8] to execute different types of algorithms that deal with the image as a whole image instead of dealing with pixels values individually. For image encryption, Chang et al al in 2009 implemented the AES algorithm on an FPGA using a Virtex22 device.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

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Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quadengine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image's part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Mohammed¹,

Amir²,

Salih³

et al. 2022

IJACSA

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“…Police and military could use frequency jamming to disturb the communication between the opponents while terrorist can use frequency jamming to prevent people from calling help from police and etc. [1].…”

Section: Introductionmentioning

confidence: 99%

“…Another major usage of frequency jamming is to jam missile(s) launched from the opponent to avoid protected target from being destroyed or to protect certain important person from being attacked. In this project, a laser missile jamming system will be designed, which has the ability to jam guiding signal of multiple missiles launched from attacker and leading the missile(s) away from the target [2].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of embedded concurrent laser missile jammer system using FPGA

Lim

Salih

2019

IJEECS

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<span>In real time system, every second takes into count as any extra delay could cause critical consequences. Nowadays, almost every system involving multiple data processing. To handle multiple data at the same time, spatial parallelism is required to enhance system performance and provide multitasking feature. Currently, frequency jamming system only can jam one signal at a time. When it comes to missile jamming, the delaying in processing the frequency could cause serious impact as there will be multiple missiles launched to hit a target. These missiles just need few seconds to hit the target within range. Laser missile jammer is designed, which can jam multiple missiles at a time from different directions. The potentials of Field Programmable Gate Array (FPGA) and spatial parallelism is used in this system, to enhance the performance of the system by increasing operating frequency, system throughput, decreasing system cost, power consumption of the system, and get lower complexity. Quartus II version 14.1 is used in this project as a development CAD tool, the entire system implemented on FPGA DE1-SoC board. Also, other components such as Laser Detector, Laser Transmitter, and monitoring screen is integrated with the board. A signal emulator module was designed, to generate signals for on-board self-testing purpose, this system can detect the frequency of laser missile and create an over-powered signal with similar frequency to jam the missile(s) through diffused plates. All the results are shown on control display. This system had achieved a better throughput and lower complexity in terms of less resource usage (3153 Logic Elements) and high operating frequency (up to 1.6 GHz).</span>

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Design and implementation computing unit for laser jamming system using spatial parallelism on FPGA

Cited by 2 publications

References 5 publications

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Design and implementation of embedded concurrent laser missile jammer system using FPGA

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