Design and implementation of a 2D convolution core for video applications on FPGAs

Benkrid, Khaled; Belkacemi, S.

doi:10.1109/dcv.2002.1218747

Cited by 17 publications

(7 citation statements)

References 3 publications

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“…With the configuration described above, the pixel processor (excluding the DMA controller and its associated FIFOs) consumes only 251 slices of the Virtex II FPGA, where each CLB contains four slices. This compares quite favorably to some other 2D convolution implementations [3] [4], which generally consume much more of the FPGA. However, our savings come at the expense of using a BRAM, of which there is a limited number.…”

Section: B Pixel Processormentioning

confidence: 76%

Fast 3D reconstruction for small autonomous robots

Cardon

Fife

Archibald

et al. 2005

31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON 2005.

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The reconstruction of the 3D structure of a static env ironm ent is a p ow erful cap ab ility ap p licab le to rob ot nav ig ation. W e p resent a nov el ap p roach to d eterm ine the 3D p ositions of a sp arse set of p oints track ed b y a sm all autonom ous rob ot in a static env ironm ent. U sing noisy feature track ing and a roug h estim ate of the essential m atrix , our m ethod has a relativ ely low com p utational cost and runs at fram e rate (1 5 fp s) on a sm all F P G A -b ased rob ot p latform . The w ork ing im p lem entation d em onstrates the p ow er of F P G A hard w are/ softw are co-d esig n in sm all rob otics app lications. In ad d ition, w e d escrib e our im p lem entation of a real-tim e im ag e d eriv ativ e com p utation sy stem for use b y our v ision alg orithm . W e p resent results of using our m ethod to nav ig ate a test env ironm ent.

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Section: B Pixel Processormentioning

confidence: 76%

Fast 3D reconstruction for small autonomous robots

Cardon

Fife

Archibald

et al. 2005

31st Annual Conference of IEEE Industrial Electronics Society, 2005. IECON 2005.

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“…Benkrid [9] proposed a 2D convolution core on FPGA in 2002. Later, Zhang [10] explored the different optimizations for FPGA-based convolution core on resource utilization, bandwidth, energy efficiency and memory access pattern.…”

Section: Related Workmentioning

confidence: 99%

“…For example, with the buffer size in equation (9), one input data is used in K 2 /S 2 MA operations during its lifetime in the buffer. However, we can see from equation (1) that one input data can be used in at most N o * K 2 /S 2 MA operations.…”

Section: E Model Modification 1) Data Reusementioning

confidence: 99%

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

Zhao

Luk

et al. 2016

2016 IEEE 27th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Abstract-This paper presents a novel reconfigurable framework for training Convolutional Neural Networks (CNNs). The proposed framework is based on reconfiguring a streaming datapath at runtime to cover the training cycle for the various layers in a CNN. The streaming datapath can support various parameterized modules which can be customized to produce implementations with different trade-offs in performance and resource usage. The modules follow the same input and output data layout, simplifying configuration scheduling. For different layers, instances of the modules contain different computation kernels in parallel, which can be customized with different layer configurations and data precision. The associated models on performance, resource and bandwidth can be used in deriving parameters for the datapath to guide the analysis of design tradeoffs to meet application requirements or platform constraints. They enable estimation of the implementation specifications given different layer configurations, to maximize performance under the constraints on bandwidth and hardware resources. Experimental results indicate that the proposed module design targeting Maxeler technology can achieve a performance of 62.06 GFLOPS for 32-bit floating-point arithmetic, outperforming existing accelerators. Further evaluation based on training LeNet-5 shows that the proposed framework achieves about 4 times faster than CPU implementation of Caffe and about 7.5 times more energy efficient than the GPU implementation of Caffe.

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“…Digital media processors with a large number of high-speed multiply-and-accumulate (MAC) units have been used to implement the convolution operation [18]. LSI architectures using a mixed analog-digital approach [20] as well as several FPGA-based implementations have also been proposed [3] [24].…”

Section: Related Workmentioning

confidence: 99%

A dynamically configurable coprocessor for convolutional neural networks

ChakradharSrimat¹,

SankaradasMurugan²,

JakkulaVenkata³

et al. 2010

SIGARCH Comput. Archit. News

150

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Convolutional neural networks (CNN) applications range from recognition and reasoning (such as handwriting recognition, facial expression recognition and video surveillance) to intelligent text applications such as semantic text analysis and natural language processing applications. Two key observations drive the design of a new architecture for CNN. First, CNN workloads exhibit a widely varying mix of three types of parallelism: parallelism within a convolution operation, intra-output parallelism where multiple input sources (features) are combined to create a single output, and inter-output parallelism where multiple, independent outputs (features) are computed simultaneously. Workloads differ significantly across different CNN applications, and across different layers of a CNN. Second, the number of processing elements in an architecture continues to scale (as per Moore's law) much faster than off-chip memory bandwidth (or pin-count) of chips. Based on these two observations, we show that for a given number of processing elements and off-chip memory bandwidth, a new CNN hardware architecture that dynamically configures the hardware on-the-fly to match the specific mix of parallelism in a given workload gives the best throughput performance. Our CNN compiler automatically translates high abstraction network specification into a parallel microprogram (a sequence of low-level VLIW instructions) that is mapped, scheduled and executed by the coprocessor. Compared to a 2.3 GHz quad-core, dual socket Intel Xeon, 1.35 GHz C870 GPU, and a 200 MHz FPGA implementation, our 120 MHz dynamically configurable architecture is 4x to 8x faster. This is the first CNN architecture to achieve real-time video stream processing (25 to 30 frames per second) on a wide range of object detection and recognition tasks.

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Design and implementation of a 2D convolution core for video applications on FPGAs

Cited by 17 publications

References 3 publications

Fast 3D reconstruction for small autonomous robots

Fast 3D reconstruction for small autonomous robots

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

A dynamically configurable coprocessor for convolutional neural networks

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