This paper presents the design and implementation of a 2 -0 convolution core for video applications optimised for the Xilinx low cost 3.3V SpartanXLTM FPGA family. The core is parameterised and scaleable in terms of the convolution window size and coeficients, the input pixel word length and the image size. The window coefficients are represented as surdsubtract of power of twos in Canonical Signed Digit (CSD) representation, which means that the usually costly multiplication operation can be easily implemented by a small number of simple shift-and-add operations, leading to considerable hardware savings. Optimised FPGA configurations capable of processing real time PAL video are automatically generated from high-level descriptions of generic 2 -0 convolutions, in the form of EDIF netlists, in less than I sec.

No abstract

No abstract

No abstract

No abstract