Design and implementation of SFQ programmable clock generators

Ito

IEEE Trans. Appl. Supercond.

et al. 2005

Self Cite

We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA cm 2 Nb standard process and the CONNECT cell library.The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip highspeed tests.

Section: On-chip High-speed Testsupporting

confidence: 80%

Advanced Design Approaches for SFQ Logic Circuits Based on the Binary Decision Diagram

Ito

IEEE Trans. Appl. Supercond.

et al. 2005

Self Cite

“…7 shows a block diagram of the SFQ clock generator investigated. The system is composed of a ring-oscillator type clock generator with a SFQ pulse counter, which generates high-frequency SFQ pulses [3], [10]. The frequency of the output SFQ pulse train is 14.6 GHz at the designed bias point.…”

Section: Demonstration Of Lr-loaded Sfq Circuitsmentioning

confidence: 99%

“…In order to measure the error rate of the clock generator, the number of output SFQ pulses was counted by another SFQ pulse counter designed using a conventional biasing technique. The -pulse generation and error check were repeated many times and the bit error rate of the clock generator was estimated [10]. Fig.…”

Section: Demonstration Of Lr-loaded Sfq Circuitsmentioning

confidence: 99%

Study of LR-Loading Technique for Low-Power Single Flux Quantum Circuits

Yamanashi

IEEE Trans. Appl. Supercond.

2007

A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.

“…The proposed TDC consists of two sets of NDRO-based ring oscillators [7] and T1-flip-flop-based binary counters [8], and a coincidence detector (CD). A block diagram and a timing chart of the TDC is shown in Figs.…”

Section: Architecture Of the Tdcmentioning

confidence: 99%

Improvement of time resolution of the double-oscillator time-to-digital converter using SFQ circuits

Nakamiya

Physica C: Superconductivity and its Applications

et al. 2007

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We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range in addition to the high resolution and the high sensitivity of the SFQ TDC compared to semiconductor TDCs. The time resolution of the proposed TDC is limited by the resolution of the CD. In order to improve the resolution, we have developed a dynamic AND (DAND) gate, which can detect two simultaneous SFQ signal inputs with high accuracy. It was demonstrated that the time resolution of the TDC using the DAND gate is improved to be ±4 ps.