Design and Implementation of Sixteen-bit Low Power and Area Efficient Dadda Multiplier

Manu, V; Prakash, A. M. Vijaya; Chandra, Mohan U

doi:10.1109/rteict46194.2019.9016834

Cited by 5 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Full adder design plays the key role in the design of all the above mentioned architectures. From the literature survey, [13][14][15][16] it has been observed that various optimizations have been performed in the design of full adder. Thus, Full adder with minimum area is taken as the basic building block from cadence encounter library and is used in the design of CSLA using ZFCLOT.…”

Section: F I G U R E 14 Comparison Of Leakage Power For Different Architecturesmentioning

confidence: 99%

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Sindhuri

Kalluru²,

Inty

2020

Computational Intelligence

View full text Add to dashboard Cite

Square Root Carry Select Adder (SQRT-CSLA) is accomplishing the noteworthy attention in the arena of VLSI (Very-Large-Scale Integration) systems as it can process the computations with high speed. Though the current trending SQRT-CSLA adder designing techniques are effective in various performance metrics, there is a possibility to improve the design addressing various performance metrics. This article proposes CSLA architecture by employing Zero Finding Logic using the Logic optimization technique (ZFCLOT). CSLA using ZFCLOT is designed, simulated, and synthesized using 90 nm cadence tools. CSLA using ZFCLOT achieves an area efficiency of 46.127% and a power efficiency of 48.4% as against to SQRT-CSLA.

show abstract

Section: F I G U R E 14 Comparison Of Leakage Power For Different Architecturesmentioning

confidence: 99%

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Sindhuri

Kalluru²,

Inty

2020

Computational Intelligence

View full text Add to dashboard Cite

show abstract

“…To reduce power and area, an optimized adder with pass transistor logic is used to design a dadda multiplier in 18 , but the output voltage levels are not as strong as in CMOS logic. The authors proposed a Dadda circuit based on the carry look-ahead adder and optimized full adder in 19 , which was implemented using complex cells in CMOS 65 nm technology.…”

Section: Introductionmentioning

confidence: 99%

Area, Delay, and Energy-Efficient Full Dadda Multiplier

Munawar

Shabbir

Akram

2023

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50[Formula: see text]nm, 90[Formula: see text]nm, and 120[Formula: see text]nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33[Formula: see text]GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50[Formula: see text]nm technology consumes 25[Formula: see text]uW of power at 3.33[Formula: see text]GHz with 76[Formula: see text]ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

show abstract

A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Ghasemi

Fathi

Mousazadeh

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThe proposed booth decoder/encoder unit is an ultrahigh‐speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 μm CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate‐level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30–200% comparing related works and also improves the delay of the multiplier 4–21%. The power consumption and the area of the structure are 477 μw and 20 × 18 μm2, respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

show abstract

Design and Implementation of Sixteen-bit Low Power and Area Efficient Dadda Multiplier

Cited by 5 publications

References 11 publications

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

Area, Delay, and Energy-Efficient Full Dadda Multiplier

A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Contact Info

Product

Resources

About